Re: [PATCH 0/4] Fix IRQ routing in via south bridge

[Mark Cave-Ayland]

On 29/10/2023 13:45, BALATON Zoltan wrote:

> On Sun, 29 Oct 2023, Mark Cave-Ayland wrote:
> > On 29/10/2023 00:56, BALATON Zoltan wrote:
> >
> > > This is going back to my otiginal proposal in
> > > https://patchew.org/QEMU/cover.1677004414.git.balaton@eik.bme.hu/
> > > implementing routing of interrupts from device functions and PCI
> > > devices to ISA interrupts. On pegasos2 the firmware sets evertyhing to
> > > share IRQ 9 so the current simpified version worked for taht but with
> > > the amigaone machine its firmware makes use of this feature and
> > > assigns different interrupts to functions and PCI devices so we need
> > > to properly impelent this.
> >
> > <quote>
> > > Since any ISA interrupt can be controlled
> > > by any interrupt source (different functions of the multifunction
> > > device plus the 4 input pins from PCI devices) there are more than 4
> > > possible sources so this can't be handled by just the 4 PCI interrupt
> > > lines. We need to keep track of the state of each interrupt source to
> > > be able to determine the level of the ISA interrupt and avoid one
> > > device clearing it while other still has an interrupt.
> > </quote>
> >
> > This here is the important bit, since what you're describing here is exactly how 
> > PCI interrupts in QEMU work, and so is already handled by the existing PCI IRQ 
> > routing code. It seems to me that what you're doing here is creating an incomplete 
> > re-implementation of part of the PCI interrupt logic in isa_irq_state, which is a 
> > strong hint that this is the wrong approach and that you should be making use of 
> > PCI IRQ routing.
>
> I don't see how this can be handled by the PCI interrupt routing which only considers 
> 4 lines while in VIA we have more sources than that which are the chip functions 
> (some even with more than one IRQ like IDE) and the 4 PCI interrupt inputs and these 
> can be routed to any of the ISA IRQs independently (there's a register for each of 
> them, the funcs use thi interrupt line config reg and the PCI pins the regs in the 
> ISA func). So how would PCI handle this when it only sees the 4 PCI interrupt lines 
> but not the chip functions as separate sources? You've assumed that those functions 
> must be PCI devices too but their interrupts are routable separately from the PCI 
> interrupts so you can have PCI INTA-D mapped to IRQ 7,8,9,10 and USB func mapped to 
> IRQ 5 (like amigaone does) so you can't use PCI interrupt for the USB too but have to 
> consider all of these separately and route them in the ISA bridge.

Ah so the restriction here is the number of PCI interrupt lines? That can be done by 
increasing the number of PCI bus IRQs to 4 + N, where 0-3 represent INTA-D and the N 
others represent individual functions on the in-built devices. You can then determine 
the slot/function in the PCI map IRQ function to route to the appropriate N IRQ.

> > > This fixes USB on amigaone and maybe other bugs not discovered yet.
> >
> > Given that the AmigaOne machine is new, can you explain in a bit more detail what 
> > the difference is between the Pegasos2 and AmigaOne machines, particularly with 
> > respect to where the existing IRQ routing logic is getting this wrong?
>
> The pegasos2 firmware sets all chip functions and PCI devices (except IDE which is 
> hard coded to legacy interrupts) to IRQ 9 so it worked with mixing PCI interrupts 
> with chip functions but the amigaone does not do that and sets different ISA 
> interrupts to chip functions and PCI interrupts so the current simplified version 
> cannot work with that any more and we need to allow separate routing of all the 
> interrupt sources. (Additionally we need to keep interrupt state for each source to 
> allow multiple sources to control the same ISA interrupt.) I could not think of any 
> simpler way than my patch to correctly implement this.

The key point of interest is that we have PIIX that basically already works using the 
existing PCI IRQ routing APIs: the aim is to do something similar with VIA, or to 
tweak the existing APIs if needed to make it possible. Otherwise you end up with the 
situation in this series in which you're effectively inventing a parallel form of PCI 
IRQ routing just for the VIA ISA bridge and hardcoding it into the in-built VIA devices.

The benefit of using the PCI IRQ routing APIs is that it is also possible to plug in 
the individual PCI device/functions using -device into any PCI bus for testing, which 
is something that is already done with PIIX-IDE.


ATB,

Mark.