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qemu-riscv (date)
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Last Modified: Tue Mar 31 2020 13:03:50 -0400
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March 31, 2020
Re: [PATCH-for-5.0 12/12] hw/riscv/sifive_u: Add missing error-propagation code
,
Peter Maydell
,
13:03
Re: [PATCH-for-5.0 12/12] hw/riscv/sifive_u: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
13:02
Re: [PATCH-for-5.0 00/12] hw: Add missing error-propagation code
,
Markus Armbruster
,
09:23
Re: [PATCH RFC 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
,
Anup Patel
,
07:19
Re: [PATCH RFC 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit
,
Anup Patel
,
05:51
RE: [PATCH RFC 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit
,
Jiangyifei
,
05:27
Re: [PATCH RFC 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
,
Anup Patel
,
05:13
Re: [PATCH RFC 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit
,
Anup Patel
,
01:16
March 30, 2020
Re: [PATCH v7 00/61] target/riscv: support vector extension v0.7.1
,
no-reply
,
19:38
[PATCH v7 61/61] target/riscv: configure and turn on vector extension from command line
,
LIU Zhiwei
,
13:39
[PATCH v7 60/61] target/riscv: vector compress instruction
,
LIU Zhiwei
,
13:38
[PATCH v7 59/61] target/riscv: vector register gather instruction
,
LIU Zhiwei
,
13:35
[PATCH v7 58/61] target/riscv: vector slide instructions
,
LIU Zhiwei
,
13:34
[PATCH v7 57/61] target/riscv: floating-point scalar move instructions
,
LIU Zhiwei
,
13:31
[PATCH v7 56/61] target/riscv: integer scalar move instruction
,
LIU Zhiwei
,
13:29
[PATCH v7 55/61] target/riscv: integer extract instruction
,
LIU Zhiwei
,
13:27
[PATCH v7 54/61] target/riscv: vector element index instruction
,
LIU Zhiwei
,
13:25
[PATCH v7 53/61] target/riscv: vector iota instruction
,
LIU Zhiwei
,
13:23
[PATCH v7 52/61] target/riscv: set-X-first mask bit
,
LIU Zhiwei
,
13:21
[PATCH v7 51/61] target/riscv: vmfirst find-first-set mask bit
,
LIU Zhiwei
,
13:19
[PATCH v7 50/61] target/riscv: vector mask population count vmpopc
,
LIU Zhiwei
,
13:17
[PATCH v7 49/61] target/riscv: vector mask-register logical instructions
,
LIU Zhiwei
,
13:15
[PATCH v7 48/61] target/riscv: vector widening floating-point reduction instructions
,
LIU Zhiwei
,
13:13
[PATCH v7 47/61] target/riscv: vector single-width floating-point reduction instructions
,
LIU Zhiwei
,
13:11
[PATCH v7 46/61] target/riscv: vector wideing integer reduction instructions
,
LIU Zhiwei
,
13:09
[PATCH v7 45/61] target/riscv: vector single-width integer reduction instructions
,
LIU Zhiwei
,
13:07
[PATCH v7 44/61] target/riscv: narrowing floating-point/integer type-convert instructions
,
LIU Zhiwei
,
13:05
[PATCH v7 43/61] target/riscv: widening floating-point/integer type-convert instructions
,
LIU Zhiwei
,
13:03
[PATCH v7 42/61] target/riscv: vector floating-point/integer type-convert instructions
,
LIU Zhiwei
,
13:01
[PATCH v7 41/61] target/riscv: vector floating-point merge instructions
,
LIU Zhiwei
,
12:59
[PATCH v7 40/61] target/riscv: vector floating-point classify instructions
,
LIU Zhiwei
,
12:57
[PATCH v7 39/61] target/riscv: vector floating-point compare instructions
,
LIU Zhiwei
,
12:55
Re: [PATCH v7 24/61] target/riscv: vector single-width saturating add and subtract
,
Alistair Francis
,
12:55
[PATCH v7 38/61] target/riscv: vector floating-point sign-injection instructions
,
LIU Zhiwei
,
12:53
[PATCH v7 37/61] target/riscv: vector floating-point min/max instructions
,
LIU Zhiwei
,
12:51
[PATCH v7 36/61] target/riscv: vector floating-point square-root instruction
,
LIU Zhiwei
,
12:49
[PATCH v7 35/61] target/riscv: vector widening floating-point fused multiply-add instructions
,
LIU Zhiwei
,
12:47
[PATCH v7 34/61] target/riscv: vector single-width floating-point fused multiply-add instructions
,
LIU Zhiwei
,
12:45
[PATCH v7 33/61] target/riscv: vector widening floating-point multiply
,
LIU Zhiwei
,
12:43
[PATCH v7 32/61] target/riscv: vector single-width floating-point multiply/divide instructions
,
LIU Zhiwei
,
12:41
[PATCH v7 31/61] target/riscv: vector widening floating-point add/subtract instructions
,
LIU Zhiwei
,
12:39
[PATCH v7 30/61] target/riscv: vector single-width floating-point add/subtract instructions
,
LIU Zhiwei
,
12:37
[PATCH v7 29/61] target/riscv: vector narrowing fixed-point clip instructions
,
LIU Zhiwei
,
12:35
Re: [PATCH] riscv: Fix Stage2 SV32 page table walk
,
Alistair Francis
,
12:33
[PATCH v7 28/61] target/riscv: vector single-width scaling shift instructions
,
LIU Zhiwei
,
12:33
[PATCH v7 27/61] target/riscv: vector widening saturating scaled multiply-add
,
LIU Zhiwei
,
12:31
[PATCH v7 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation
,
LIU Zhiwei
,
12:29
[PATCH v7 25/61] target/riscv: vector single-width averaging add and subtract
,
LIU Zhiwei
,
12:27
[PATCH v7 24/61] target/riscv: vector single-width saturating add and subtract
,
LIU Zhiwei
,
12:25
[PATCH v7 23/61] target/riscv: vector integer merge and move instructions
,
LIU Zhiwei
,
12:23
[PATCH v7 22/61] target/riscv: vector widening integer multiply-add instructions
,
LIU Zhiwei
,
12:21
[PATCH v7 21/61] target/riscv: vector single-width integer multiply-add instructions
,
LIU Zhiwei
,
12:19
[PATCH v7 20/61] target/riscv: vector widening integer multiply instructions
,
LIU Zhiwei
,
12:17
[PATCH v7 19/61] target/riscv: vector integer divide instructions
,
LIU Zhiwei
,
12:15
[PATCH v7 18/61] target/riscv: vector single-width integer multiply instructions
,
LIU Zhiwei
,
12:13
[PATCH v7 17/61] target/riscv: vector integer min/max instructions
,
LIU Zhiwei
,
12:11
[PATCH v7 16/61] target/riscv: vector integer comparison instructions
,
LIU Zhiwei
,
12:09
[PATCH v7 15/61] target/riscv: vector narrowing integer right shift instructions
,
LIU Zhiwei
,
12:07
[PATCH v7 14/61] target/riscv: vector single-width bit shift instructions
,
LIU Zhiwei
,
12:05
[PATCH v7 13/61] target/riscv: vector bitwise logical instructions
,
LIU Zhiwei
,
12:03
[PATCH v7 12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
,
LIU Zhiwei
,
12:01
[PATCH v7 11/61] target/riscv: vector widening integer add and subtract
,
LIU Zhiwei
,
11:59
[PATCH v7 10/61] target/riscv: vector single-width integer add and subtract
,
LIU Zhiwei
,
11:57
[PATCH v7 09/61] target/riscv: add vector amo operations
,
LIU Zhiwei
,
11:55
[PATCH v7 08/61] target/riscv: add fault-only-first unit stride load
,
LIU Zhiwei
,
11:53
[PATCH v7 07/61] target/riscv: add vector index load and store instructions
,
LIU Zhiwei
,
11:51
[PATCH v7 06/61] target/riscv: add vector stride load and store instructions
,
LIU Zhiwei
,
11:49
[PATCH v7 05/61] target/riscv: add an internals.h header
,
LIU Zhiwei
,
11:47
[PATCH v7 04/61] target/riscv: add vector configure instruction
,
LIU Zhiwei
,
11:45
[PATCH v7 03/61] target/riscv: support vector extension csr
,
LIU Zhiwei
,
11:43
[PATCH v7 02/61] target/riscv: implementation-defined constant parameters
,
LIU Zhiwei
,
11:41
[PATCH v7 01/61] target/riscv: add vector extension field in CPURISCVState
,
LIU Zhiwei
,
11:39
[PATCH v7 00/61] target/riscv: support vector extension v0.7.1
,
LIU Zhiwei
,
11:37
Re: [PATCH-for-5.0 00/12] hw: Add missing error-propagation code
,
Stefan Hajnoczi
,
05:22
[PATCH] riscv: Fix Stage2 SV32 page table walk
,
Anup Patel
,
04:28
Re: [PATCH for 5.0 v1 0/2] RISC-V: Fix Hypervisor guest user space
,
Anup Patel
,
00:23
March 29, 2020
Re: [PATCH v6 18/61] target/riscv: vector single-width integer multiply instructions
,
LIU Zhiwei
,
00:00
March 28, 2020
Re: [PATCH v6 57/61] target/riscv: floating-point scalar move instructions
,
LIU Zhiwei
,
12:31
Re: [PATCH v6 55/61] target/riscv: integer extract instruction
,
LIU Zhiwei
,
12:23
Re: [PATCH v6 18/61] target/riscv: vector single-width integer multiply instructions
,
LIU Zhiwei
,
12:14
Re: [PATCH v6 41/61] target/riscv: vector floating-point merge instructions
,
LIU Zhiwei
,
11:48
Re: [PATCH v6 18/61] target/riscv: vector single-width integer multiply instructions
,
Richard Henderson
,
11:47
Re: [PATCH v6 39/61] target/riscv: vector floating-point compare instructions
,
LIU Zhiwei
,
11:45
Re: [PATCH v6 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation
,
LIU Zhiwei
,
11:41
Re: [PATCH v6 25/61] target/riscv: vector single-width averaging add and subtract
,
LIU Zhiwei
,
11:37
Re: [PATCH v6 18/61] target/riscv: vector single-width integer multiply instructions
,
LIU Zhiwei
,
11:17
Re: [PATCH v6 10/61] target/riscv: vector single-width integer add and subtract
,
LIU Zhiwei
,
10:43
Re: [PATCH v6 58/61] target/riscv: vector slide instructions
,
LIU Zhiwei
,
09:40
Re: [PATCH v6 61/61] target/riscv: configure and turn on vector extension from command line
,
Richard Henderson
,
00:00
March 27, 2020
Re: [PATCH v6 59/61] target/riscv: vector register gather instruction
,
Richard Henderson
,
23:58
Re: [PATCH v6 58/61] target/riscv: vector slide instructions
,
Richard Henderson
,
23:50
Re: [PATCH v6 57/61] target/riscv: floating-point scalar move instructions
,
Richard Henderson
,
23:44
Re: [PATCH v6 55/61] target/riscv: integer extract instruction
,
Richard Henderson
,
23:36
Re: [PATCH v6 41/61] target/riscv: vector floating-point merge instructions
,
Richard Henderson
,
23:23
Re: [PATCH v6 40/61] target/riscv: vector floating-point classify instructions
,
Richard Henderson
,
22:06
Re: [PATCH v6 39/61] target/riscv: vector floating-point compare instructions
,
Richard Henderson
,
22:02
Re: [PATCH v6 29/61] target/riscv: vector narrowing fixed-point clip instructions
,
Richard Henderson
,
21:50
Re: [PATCH v6 28/61] target/riscv: vector single-width scaling shift instructions
,
Richard Henderson
,
21:24
Re: [PATCH v6 27/61] target/riscv: vector widening saturating scaled multiply-add
,
Richard Henderson
,
21:23
Re: [PATCH v6 25/61] target/riscv: vector single-width averaging add and subtract
,
Richard Henderson
,
21:22
Re: [PATCH v6 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation
,
Richard Henderson
,
21:09
Re: [PATCH v6 25/61] target/riscv: vector single-width averaging add and subtract
,
LIU Zhiwei
,
21:07
Re: [PATCH v6 25/61] target/riscv: vector single-width averaging add and subtract
,
Richard Henderson
,
20:32
Re: [PATCH v6 24/61] target/riscv: vector single-width saturating add and subtract
,
Richard Henderson
,
20:20
Re: [PATCH v6 23/61] target/riscv: vector integer merge and move instructions
,
Richard Henderson
,
20:18
Re: [PATCH v6 18/61] target/riscv: vector single-width integer multiply instructions
,
Richard Henderson
,
20:06
Re: [PATCH v6 12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
,
Richard Henderson
,
20:00
Re: [PATCH v6 10/61] target/riscv: vector single-width integer add and subtract
,
Richard Henderson
,
19:54
Re: [PATCH v6 09/61] target/riscv: add vector amo operations
,
Richard Henderson
,
19:45
Re: [PATCH v6 05/61] target/riscv: add an internals.h header
,
Richard Henderson
,
19:41
March 26, 2020
Re: [PATCH-for-5.0 08/12] hw/mips/boston: Add missing error-propagation code
,
Aleksandar Markovic
,
20:22
Re: [PATCH-for-5.0 07/12] hw/mips/cps: Add missing error-propagation code
,
Aleksandar Markovic
,
20:22
Re: [PATCH-for-5.0 09/12] hw/mips/mips_malta: Add missing error-propagation code
,
Aleksandar Markovic
,
20:22
Re: [PATCH for 5.0 v1 0/2] RISC-V: Fix Hypervisor guest user space
,
Palmer Dabbelt
,
20:00
Re: [PATCH for 5.0 v1 2/2] riscv: AND stage-1 and stage-2 protection flags
,
Alistair Francis
,
19:53
Re: [PATCH for 5.0 v1 1/2] riscv: Don't use stage-2 PTE lookup protection flags
,
Richard Henderson
,
19:50
Re: [PATCH for 5.0 v1 2/2] riscv: AND stage-1 and stage-2 protection flags
,
Richard Henderson
,
19:32
[PATCH for 5.0 v1 2/2] riscv: AND stage-1 and stage-2 protection flags
,
Alistair Francis
,
18:51
[PATCH for 5.0 v1 0/2] RISC-V: Fix Hypervisor guest user space
,
Alistair Francis
,
18:51
[PATCH for 5.0 v1 1/2] riscv: Don't use stage-2 PTE lookup protection flags
,
Alistair Francis
,
18:51
Re: [PATCH-for-5.0 12/12] hw/riscv/sifive_u: Add missing error-propagation code
,
Peter Maydell
,
17:55
Re: [PATCH-for-5.0 11/12] hw/net/xilinx_axienet: Add missing error-propagation code
,
Peter Maydell
,
17:51
Re: [PATCH-for-5.0 10/12] hw/misc/macio/macio: Add missing error-propagation code
,
Peter Maydell
,
17:50
Re: [PATCH-for-5.0 09/12] hw/mips/mips_malta: Add missing error-propagation code
,
Peter Maydell
,
17:50
Re: [PATCH-for-5.0 08/12] hw/mips/boston: Add missing error-propagation code
,
Peter Maydell
,
17:48
Re: [PATCH-for-5.0 06/12] hw/dma/xilinx_axidma: Add missing error-propagation code
,
Peter Maydell
,
17:46
Re: [PATCH-for-5.0 04/12] hw/arm/stm32fx05_soc: Add missing error-propagation code
,
Peter Maydell
,
17:45
Re: [PATCH-for-5.0 07/12] hw/mips/cps: Add missing error-propagation code
,
Peter Maydell
,
17:44
Re: [PATCH-for-5.0 05/12] hw/i386/x86: Add missing error-propagation code
,
Peter Maydell
,
17:39
Re: [PATCH-for-5.0 03/12] hw/arm/fsl-imx: Add missing error-propagation code
,
Peter Maydell
,
17:35
Re: [PATCH-for-5.0 02/12] hw/arm/bcm2835_peripherals: Add missing error-propagation code
,
Peter Maydell
,
17:34
Re: [PATCH-for-5.0 01/12] scripts/coccinelle: Add script to catch missing error_propagate() calls
,
Peter Maydell
,
17:32
Re: [PATCH v6 23/61] target/riscv: vector integer merge and move instructions
,
Alistair Francis
,
14:06
Re: [PATCH v9 3/4] linux-user: Support futex_time64
,
Alistair Francis
,
12:54
Re: [PATCH v9 3/4] linux-user: Support futex_time64
,
Laurent Vivier
,
02:23
March 25, 2020
Re: [PATCH-for-5.0 10/12] hw/misc/macio/macio: Add missing error-propagation code
,
David Gibson
,
20:38
Re: [PATCH-for-5.0 12/12] hw/riscv/sifive_u: Add missing error-propagation code
,
Alistair Francis
,
17:01
Re: [PATCH-for-5.0 11/12] hw/net/xilinx_axienet: Add missing error-propagation code
,
Alistair Francis
,
17:00
Re: [PATCH-for-5.0 06/12] hw/dma/xilinx_axidma: Add missing error-propagation code
,
Alistair Francis
,
17:00
Re: [PATCH-for-5.0 04/12] hw/arm/stm32fx05_soc: Add missing error-propagation code
,
Alistair Francis
,
16:59
Re: [PATCH-for-5.0 00/12] hw: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
15:21
[PATCH-for-5.0 12/12] hw/riscv/sifive_u: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
15:19
[PATCH-for-5.0 11/12] hw/net/xilinx_axienet: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
15:19
[PATCH-for-5.0 03/12] hw/arm/fsl-imx: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
15:19
[PATCH-for-5.0 10/12] hw/misc/macio/macio: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
15:19
[PATCH-for-5.0 09/12] hw/mips/mips_malta: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
15:19
[PATCH-for-5.0 08/12] hw/mips/boston: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
15:19
[PATCH-for-5.0 07/12] hw/mips/cps: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
15:19
[PATCH-for-5.0 06/12] hw/dma/xilinx_axidma: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
15:19
[PATCH-for-5.0 04/12] hw/arm/stm32fx05_soc: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
15:19
[PATCH-for-5.0 05/12] hw/i386/x86: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
15:19
[PATCH-for-5.0 02/12] hw/arm/bcm2835_peripherals: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
15:18
[PATCH-for-5.0 01/12] scripts/coccinelle: Add script to catch missing error_propagate() calls
,
Philippe Mathieu-Daudé
,
15:18
[PATCH-for-5.0 00/12] hw: Add missing error-propagation code
,
Philippe Mathieu-Daudé
,
15:18
Re: [PATCH v6 61/61] target/riscv: configure and turn on vector extension from command line
,
Alistair Francis
,
13:57
Re: [PATCH v6 37/61] target/riscv: vector floating-point min/max instructions
,
Alistair Francis
,
13:56
Re: [PATCH v6 32/61] target/riscv: vector single-width floating-point multiply/divide instructions
,
Alistair Francis
,
13:54
Re: [PATCH v6 22/61] target/riscv: vector widening integer multiply-add instructions
,
Alistair Francis
,
13:50
Re: [PATCH v9 3/4] linux-user: Support futex_time64
,
Alistair Francis
,
13:49
Re: [PATCH v6 18/61] target/riscv: vector single-width integer multiply instructions
,
Alistair Francis
,
13:44
Re: [PATCH v6 16/61] target/riscv: vector integer comparison instructions
,
Alistair Francis
,
13:40
Re: [PATCH v6 21/61] target/riscv: vector single-width integer multiply-add instructions
,
Alistair Francis
,
13:36
Re: [PATCH v6 20/61] target/riscv: vector widening integer multiply instructions
,
Alistair Francis
,
13:33
March 24, 2020
Re: [PATCH v5 57/60] target/riscv: vector slide instructions
,
Richard Henderson
,
10:52
Re: [PATCH v5 57/60] target/riscv: vector slide instructions
,
LIU Zhiwei
,
06:51
March 23, 2020
Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
,
Bin Meng
,
22:08
Re: [PATCH v5 09/60] target/riscv: vector single-width integer add and subtract
,
Richard Henderson
,
13:47
Re: [PATCH v5 09/60] target/riscv: vector single-width integer add and subtract
,
LIU Zhiwei
,
04:10
Re: [PATCH v6 04/61] target/riscv: add vector configure instruction
,
LIU Zhiwei
,
03:10
Re: [PATCH v6 04/61] target/riscv: add vector configure instruction
,
Kito Cheng
,
02:51
March 20, 2020
Re: [PATCH v6 19/61] target/riscv: vector integer divide instructions
,
Alistair Francis
,
14:59
Re: [PATCH v6 17/61] target/riscv: vector integer min/max instructions
,
Alistair Francis
,
14:57
Re: [PATCH v6 15/61] target/riscv: vector narrowing integer right shift instructions
,
Alistair Francis
,
14:51
Re: [PATCH v6 13/61] target/riscv: vector bitwise logical instructions
,
Alistair Francis
,
14:43
Re: [PATCH v6 10/61] target/riscv: vector single-width integer add and subtract
,
Alistair Francis
,
14:39
March 19, 2020
Re: [PATCH v6 14/61] target/riscv: vector single-width bit shift instructions
,
Alistair Francis
,
16:19
Re: [PATCH v6 12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
,
Alistair Francis
,
13:37
Re: [PATCH v6 09/61] target/riscv: add vector amo operations
,
Alistair Francis
,
13:10
Re: [PATCH v6 11/61] target/riscv: vector widening integer add and subtract
,
Alistair Francis
,
12:36
Re: [PATCH v1 1/1] target/riscv: Don't set write permissions on dirty PTEs
,
Alistair Francis
,
12:04
Re: [PATCH v1 1/1] target/riscv: Don't set write permissions on dirty PTEs
,
Palmer Dabbelt
,
00:52
March 18, 2020
Re: [PATCH v6 25/61] target/riscv: vector single-width averaging add and subtract
,
LIU Zhiwei
,
23:47
Re: [PATCH v9 0/4] linux-user: generate syscall_nr.sh for RISC-V
,
no-reply
,
21:13
Re: [PATCH v9 0/4] linux-user: generate syscall_nr.sh for RISC-V
,
no-reply
,
20:39
Re: [PATCH v6 06/61] target/riscv: add vector stride load and store instructions
,
Alistair Francis
,
20:03
Re: [PATCH v6 05/61] target/riscv: add an internals.h header
,
Alistair Francis
,
19:53
Re: [PATCH v9 2/4] linux-user/syscall: Add support for clock_gettime64/clock_settime64
,
Philippe Mathieu-Daudé
,
19:36
Re: [PATCH v9 1/4] linux-user: Protect more syscalls
,
Philippe Mathieu-Daudé
,
19:32
[PATCH v9 4/4] linux-user/riscv: Update the syscall_nr's to the 5.5 kernel
,
Alistair Francis
,
18:55
[PATCH v9 3/4] linux-user: Support futex_time64
,
Alistair Francis
,
18:54
[PATCH v9 1/4] linux-user: Protect more syscalls
,
Alistair Francis
,
18:54
[PATCH v9 2/4] linux-user/syscall: Add support for clock_gettime64/clock_settime64
,
Alistair Francis
,
18:54
[PATCH v9 0/4] linux-user: generate syscall_nr.sh for RISC-V
,
Alistair Francis
,
18:54
March 17, 2020
Re: [PATCH v6 00/61] target/riscv: support vector extension v0.7.1
,
no-reply
,
16:47
[PULL 14/28] gdbstub: extend GByteArray to read register helpers
,
Alex Bennée
,
13:51
[PATCH v6 61/61] target/riscv: configure and turn on vector extension from command line
,
LIU Zhiwei
,
13:10
[PATCH v6 60/61] target/riscv: vector compress instruction
,
LIU Zhiwei
,
13:08
[PATCH v6 59/61] target/riscv: vector register gather instruction
,
LIU Zhiwei
,
13:06
[PATCH v6 58/61] target/riscv: vector slide instructions
,
LIU Zhiwei
,
13:04
[PATCH v6 57/61] target/riscv: floating-point scalar move instructions
,
LIU Zhiwei
,
13:02
[PATCH v6 56/61] target/riscv: integer scalar move instruction
,
LIU Zhiwei
,
13:00
[PATCH v6 55/61] target/riscv: integer extract instruction
,
LIU Zhiwei
,
12:58
[PATCH v6 54/61] target/riscv: vector element index instruction
,
LIU Zhiwei
,
12:56
[PATCH v6 53/61] target/riscv: vector iota instruction
,
LIU Zhiwei
,
12:54
[PATCH v6 52/61] target/riscv: set-X-first mask bit
,
LIU Zhiwei
,
12:52
[PATCH v6 51/61] target/riscv: vmfirst find-first-set mask bit
,
LIU Zhiwei
,
12:49
[PATCH v6 50/61] target/riscv: vector mask population count vmpopc
,
LIU Zhiwei
,
12:47
[PATCH v6 49/61] target/riscv: vector mask-register logical instructions
,
LIU Zhiwei
,
12:46
[PATCH v6 48/61] target/riscv: vector widening floating-point reduction instructions
,
LIU Zhiwei
,
12:44
[PATCH v6 47/61] target/riscv: vector single-width floating-point reduction instructions
,
LIU Zhiwei
,
12:41
[PATCH v6 46/61] target/riscv: vector wideing integer reduction instructions
,
LIU Zhiwei
,
12:39
[PATCH v6 45/61] target/riscv: vector single-width integer reduction instructions
,
LIU Zhiwei
,
12:38
[PATCH v6 44/61] target/riscv: narrowing floating-point/integer type-convert instructions
,
LIU Zhiwei
,
12:35
[PATCH v6 43/61] target/riscv: widening floating-point/integer type-convert instructions
,
LIU Zhiwei
,
12:33
[PATCH v6 42/61] target/riscv: vector floating-point/integer type-convert instructions
,
LIU Zhiwei
,
12:31
[PATCH v6 41/61] target/riscv: vector floating-point merge instructions
,
LIU Zhiwei
,
12:29
[PATCH v6 40/61] target/riscv: vector floating-point classify instructions
,
LIU Zhiwei
,
12:27
[PATCH v6 39/61] target/riscv: vector floating-point compare instructions
,
LIU Zhiwei
,
12:26
[PATCH v6 38/61] target/riscv: vector floating-point sign-injection instructions
,
LIU Zhiwei
,
12:23
[PATCH v6 37/61] target/riscv: vector floating-point min/max instructions
,
LIU Zhiwei
,
12:21
[PATCH v6 36/61] target/riscv: vector floating-point square-root instruction
,
LIU Zhiwei
,
12:19
[PATCH v6 35/61] target/riscv: vector widening floating-point fused multiply-add instructions
,
LIU Zhiwei
,
12:18
[PATCH v6 34/61] target/riscv: vector single-width floating-point fused multiply-add instructions
,
LIU Zhiwei
,
12:15
[PATCH v6 33/61] target/riscv: vector widening floating-point multiply
,
LIU Zhiwei
,
12:13
[PATCH v6 32/61] target/riscv: vector single-width floating-point multiply/divide instructions
,
LIU Zhiwei
,
12:11
[PATCH v6 31/61] target/riscv: vector widening floating-point add/subtract instructions
,
LIU Zhiwei
,
12:09
[PATCH v6 30/61] target/riscv: vector single-width floating-point add/subtract instructions
,
LIU Zhiwei
,
12:07
[PATCH v6 29/61] target/riscv: vector narrowing fixed-point clip instructions
,
LIU Zhiwei
,
12:05
[PATCH v6 28/61] target/riscv: vector single-width scaling shift instructions
,
LIU Zhiwei
,
12:03
[PATCH v6 27/61] target/riscv: vector widening saturating scaled multiply-add
,
LIU Zhiwei
,
12:02
[PATCH v6 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation
,
LIU Zhiwei
,
11:59
[PATCH v6 25/61] target/riscv: vector single-width averaging add and subtract
,
LIU Zhiwei
,
11:57
[PATCH v6 24/61] target/riscv: vector single-width saturating add and subtract
,
LIU Zhiwei
,
11:55
[PATCH v6 23/61] target/riscv: vector integer merge and move instructions
,
LIU Zhiwei
,
11:53
[PATCH v6 22/61] target/riscv: vector widening integer multiply-add instructions
,
LIU Zhiwei
,
11:51
[PATCH v6 21/61] target/riscv: vector single-width integer multiply-add instructions
,
LIU Zhiwei
,
11:49
[PATCH v6 20/61] target/riscv: vector widening integer multiply instructions
,
LIU Zhiwei
,
11:47
[PATCH v6 19/61] target/riscv: vector integer divide instructions
,
LIU Zhiwei
,
11:45
[PATCH v6 18/61] target/riscv: vector single-width integer multiply instructions
,
LIU Zhiwei
,
11:43
[PATCH v6 17/61] target/riscv: vector integer min/max instructions
,
LIU Zhiwei
,
11:41
[PATCH v6 16/61] target/riscv: vector integer comparison instructions
,
LIU Zhiwei
,
11:39
[PATCH v6 15/61] target/riscv: vector narrowing integer right shift instructions
,
LIU Zhiwei
,
11:37
[PATCH v6 14/61] target/riscv: vector single-width bit shift instructions
,
LIU Zhiwei
,
11:35
[PATCH v6 13/61] target/riscv: vector bitwise logical instructions
,
LIU Zhiwei
,
11:33
[PATCH v6 12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
,
LIU Zhiwei
,
11:31
[PATCH v6 11/61] target/riscv: vector widening integer add and subtract
,
LIU Zhiwei
,
11:29
[PATCH v6 10/61] target/riscv: vector single-width integer add and subtract
,
LIU Zhiwei
,
11:27
[PATCH v6 09/61] target/riscv: add vector amo operations
,
LIU Zhiwei
,
11:25
[PATCH v6 08/61] target/riscv: add fault-only-first unit stride load
,
LIU Zhiwei
,
11:23
[PATCH v6 07/61] target/riscv: add vector index load and store instructions
,
LIU Zhiwei
,
11:21
[PATCH v6 06/61] target/riscv: add vector stride load and store instructions
,
LIU Zhiwei
,
11:19
[PATCH v6 05/61] target/riscv: add an internals.h header
,
LIU Zhiwei
,
11:17
[PATCH v6 04/61] target/riscv: add vector configure instruction
,
LIU Zhiwei
,
11:15
[PATCH v6 03/61] target/riscv: support vector extension csr
,
LIU Zhiwei
,
11:13
Re: [PATCH v5 56/60] target/riscv: floating-point scalar move instructions
,
Richard Henderson
,
11:11
[PATCH v6 02/61] target/riscv: implementation-defined constant parameters
,
LIU Zhiwei
,
11:11
[PATCH v6 01/61] target/riscv: add vector extension field in CPURISCVState
,
LIU Zhiwei
,
11:09
[PATCH v6 00/61] target/riscv: support vector extension v0.7.1
,
LIU Zhiwei
,
11:07
Re: [PATCH] cpu: Use DeviceClass reset instead of a special CPUClass reset
,
Eduardo Habkost
,
10:36
Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 5
,
Peter Maydell
,
08:58
Re: [PATCH] cpu: Use DeviceClass reset instead of a special CPUClass reset
,
Peter Maydell
,
07:09
Re: [PATCH] cpu: Use DeviceClass reset instead of a special CPUClass reset
,
Philippe Mathieu-Daudé
,
07:01
Re: [PATCH v5 56/60] target/riscv: floating-point scalar move instructions
,
LIU Zhiwei
,
02:02
[PULL 2/6] roms: opensbi: Upgrade from v0.5 to v0.6
,
Palmer Dabbelt
,
00:06
[PULL 3/6] roms: opensbi: Add 32-bit firmware image for sifive_u machine
,
Palmer Dabbelt
,
00:06
[PULL 5/6] gitlab-ci.yml: Add jobs to build OpenSBI firmware binaries
,
Palmer Dabbelt
,
00:06
[PULL 6/6] target/riscv: Fix VS mode interrupts forwarding.
,
Palmer Dabbelt
,
00:06
[PULL 4/6] riscv: sifive_u: Update BIOS_FILENAME for 32-bit
,
Palmer Dabbelt
,
00:06
[PULL 1/6] target/riscv: Correctly implement TSR trap
,
Palmer Dabbelt
,
00:06
[PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 5
,
Palmer Dabbelt
,
00:06
March 16, 2020
Re: [PATCH v3 20/25] hw/riscv: Let devices own the MemoryRegion they create
,
Alistair Francis
,
14:58
[PATCH v3 20/25] hw/riscv: Let devices own the MemoryRegion they create
,
Philippe Mathieu-Daudé
,
14:52
[PATCH v3 11/25] hw/riscv: Use memory_region_init_rom() with read-only regions
,
Philippe Mathieu-Daudé
,
14:51
Re: [PATCH v5 57/60] target/riscv: vector slide instructions
,
Richard Henderson
,
13:43
[PATCH v1 14/28] gdbstub: extend GByteArray to read register helpers
,
Alex Bennée
,
13:22
Re: [PATCH v5 57/60] target/riscv: vector slide instructions
,
LIU Zhiwei
,
04:05
Re: [PATCH v5 40/60] target/riscv: vector floating-point merge instructions
,
Richard Henderson
,
01:37
Re: [PATCH v5 22/60] target/riscv: vector integer merge and move instructions
,
Richard Henderson
,
01:33
March 15, 2020
Re: [PATCH v5 40/60] target/riscv: vector floating-point merge instructions
,
LIU Zhiwei
,
23:41
Re: [PATCH v5 22/60] target/riscv: vector integer merge and move instructions
,
LIU Zhiwei
,
22:57
[PATCH v2 07/12] target/riscv/cpu: Restrict CPU migration to system-mode
,
Philippe Mathieu-Daudé
,
19:58
Re: [PATCH v5 24/60] target/riscv: vector single-width averaging add and subtract
,
Richard Henderson
,
19:27
Re: [PATCH v5 24/60] target/riscv: vector single-width averaging add and subtract
,
LIU Zhiwei
,
19:23
Re: [PATCH 01/14] Makefile: Only build virtiofsd if system-mode is enabled
,
Richard Henderson
,
18:33
Re: [PATCH 09/14] exec: Drop redundant #ifdeffery
,
Philippe Mathieu-Daudé
,
18:20
Re: [PATCH 01/14] Makefile: Only build virtiofsd if system-mode is enabled
,
Philippe Mathieu-Daudé
,
18:16
Re: [PATCH 14/14] hw/core: Restrict CpuClass::get_crash_info() to system-mode
,
Richard Henderson
,
17:03
Re: [PATCH 13/14] target/s390x: Restrict CpuClass::get_crash_info() to system-mode
,
Richard Henderson
,
16:47
Re: [PATCH 12/14] target/i386: Restrict CpuClass::get_crash_info() to system-mode
,
Richard Henderson
,
16:46
Re: [PATCH 11/14] target: Restrict write_elfXX_note() handlers to system-mode
,
Richard Henderson
,
16:44
Re: [PATCH 10/14] arch_init: Remove unused 'qapi-commands-misc.h' include
,
Richard Henderson
,
16:41
Re: [PATCH 09/14] exec: Drop redundant #ifdeffery
,
Richard Henderson
,
16:40
Re: [PATCH 08/14] exec: Assert CPU migration is not used on user-only build
,
Richard Henderson
,
16:19
Re: [PATCH 07/14] target/riscv/cpu: Restrict CPU migration to system-mode
,
Richard Henderson
,
16:18
Re: [PATCH 06/14] util/Makefile: Reduce the user-mode object list
,
Richard Henderson
,
16:18
Re: [PATCH 05/14] stubs/Makefile: Reduce the user-mode object list
,
Richard Henderson
,
16:18
Re: [PATCH 04/14] tests/Makefile: Restrict some softmmu-only tests
,
Richard Henderson
,
16:17
Re: [PATCH 04/14] tests/Makefile: Restrict some softmmu-only tests
,
Richard Henderson
,
16:07
Re: [PATCH 01/14] Makefile: Only build virtiofsd if system-mode is enabled
,
Richard Henderson
,
15:40
Re: [PATCH 03/14] tests/Makefile: Only display TCG-related tests when TCG is available
,
Richard Henderson
,
14:57
Re: [PATCH 02/14] configure: Avoid building TCG when not needed
,
Richard Henderson
,
14:56
Re: [PATCH v5 59/60] target/riscv: vector compress instruction
,
Richard Henderson
,
03:34
Re: [PATCH v5 51/60] target/riscv: set-X-first mask bit
,
Richard Henderson
,
03:26
Re: [PATCH v5 35/60] target/riscv: vector floating-point square-root instruction
,
Richard Henderson
,
03:00
Re: [PATCH v5 57/60] target/riscv: vector slide instructions
,
Richard Henderson
,
02:56
Re: [PATCH v5 57/60] target/riscv: vector slide instructions
,
LIU Zhiwei
,
02:49
Re: [PATCH v5 56/60] target/riscv: floating-point scalar move instructions
,
Richard Henderson
,
02:48
Re: [PATCH v5 56/60] target/riscv: floating-point scalar move instructions
,
LIU Zhiwei
,
02:14
Re: [PATCH v5 58/60] target/riscv: vector register gather instruction
,
Richard Henderson
,
01:44
Re: [PATCH v5 54/60] target/riscv: integer extract instruction
,
Richard Henderson
,
01:21
Re: [PATCH v5 57/60] target/riscv: vector slide instructions
,
Richard Henderson
,
01:16
Re: [PATCH v5 54/60] target/riscv: integer extract instruction
,
LIU Zhiwei
,
01:16
Re: [PATCH v5 56/60] target/riscv: floating-point scalar move instructions
,
Richard Henderson
,
00:39
March 14, 2020
Re: [PATCH v5 55/60] target/riscv: integer scalar move instruction
,
Richard Henderson
,
23:54
Re: [PATCH v5 54/60] target/riscv: integer extract instruction
,
Richard Henderson
,
22:53
Re: [PATCH v5 53/60] target/riscv: vector element index instruction
,
Richard Henderson
,
21:54
Re: [PATCH v5 52/60] target/riscv: vector iota instruction
,
Richard Henderson
,
21:50
Re: [PATCH v5 50/60] target/riscv: vmfirst find-first-set mask bit
,
Richard Henderson
,
21:36
Re: [PATCH v5 49/60] target/riscv: vector mask population count vmpopc
,
Richard Henderson
,
21:20
Re: [PATCH v5 24/60] target/riscv: vector single-width averaging add and subtract
,
Richard Henderson
,
21:01
Re: [PATCH v5 47/60] target/riscv: vector widening floating-point reduction instructions
,
Richard Henderson
,
19:49
Re: [PATCH v5 46/60] target/riscv: vector single-width floating-point reduction instructions
,
Richard Henderson
,
19:48
Re: [PATCH v5 45/60] target/riscv: vector wideing integer reduction instructions
,
Richard Henderson
,
19:34
Re: [PATCH v5 44/60] target/riscv: vector single-width integer reduction instructions
,
Richard Henderson
,
19:29
Re: [PATCH v5 24/60] target/riscv: vector single-width averaging add and subtract
,
LIU Zhiwei
,
19:13
Re: [PATCH v5 43/60] target/riscv: narrowing floating-point/integer type-convert instructions
,
Richard Henderson
,
19:08
Re: [PATCH v5 42/60] target/riscv: widening floating-point/integer type-convert instructions
,
Richard Henderson
,
19:03
Re: [PATCH v5 41/60] target/riscv: vector floating-point/integer type-convert instructions
,
Richard Henderson
,
18:50
Re: [PATCH v5 40/60] target/riscv: vector floating-point merge instructions
,
Richard Henderson
,
18:47
Re: [PATCH v5 39/60] target/riscv: vector floating-point classify instructions
,
Richard Henderson
,
18:06
Re: [PATCH v8 3/4] linux-user: Support futex_time64
,
Laurent Vivier
,
07:19
Re: [PATCH v8 3/4] linux-user: Support futex_time64
,
Laurent Vivier
,
07:05
Re: [PATCH v5 39/60] target/riscv: vector floating-point classify instructions
,
LIU Zhiwei
,
05:15
Re: [PATCH v5 38/60] target/riscv: vector floating-point compare instructions
,
LIU Zhiwei
,
05:11
Re: [PATCH v5 39/60] target/riscv: vector floating-point classify instructions
,
Richard Henderson
,
05:11
Re: [PATCH v5 38/60] target/riscv: vector floating-point compare instructions
,
Richard Henderson
,
05:08
Re: [PATCH v5 37/60] target/riscv: vector floating-point sign-injection instructions
,
Richard Henderson
,
04:57
Re: [PATCH v5 36/60] target/riscv: vector floating-point min/max instructions
,
Richard Henderson
,
04:52
Re: [PATCH v5 34/60] target/riscv: vector widening floating-point fused multiply-add instructions
,
Richard Henderson
,
04:50
Re: [PATCH v5 33/60] target/riscv: vector single-width floating-point fused multiply-add instructions
,
Richard Henderson
,
04:49
Re: [PATCH v5 32/60] target/riscv: vector widening floating-point multiply
,
Richard Henderson
,
04:46
Re: [PATCH v5 31/60] target/riscv: vector single-width floating-point multiply/divide instructions
,
Richard Henderson
,
04:44
Re: [PATCH v5 30/60] target/riscv: vector widening floating-point add/subtract instructions
,
Richard Henderson
,
04:43
Re: [PATCH v5 29/60] target/riscv: vector single-width floating-point add/subtract instructions
,
Richard Henderson
,
04:40
Re: [PATCH v5 28/60] target/riscv: vector narrowing fixed-point clip instructions
,
Richard Henderson
,
04:36
Re: [PATCH v5 27/60] target/riscv: vector single-width scaling shift instructions
,
Richard Henderson
,
04:34
Re: [PATCH v5 26/60] target/riscv: vector widening saturating scaled multiply-add
,
Richard Henderson
,
04:33
Re: [PATCH v5 25/60] target/riscv: vector single-width fractional multiply with rounding and saturation
,
Richard Henderson
,
04:27
Re: [PATCH v5 24/60] target/riscv: vector single-width averaging add and subtract
,
Richard Henderson
,
04:25
Re: [PATCH v5 24/60] target/riscv: vector single-width averaging add and subtract
,
Richard Henderson
,
04:14
Re: [PATCH v5 09/60] target/riscv: vector single-width integer add and subtract
,
LIU Zhiwei
,
04:11
Re: [PATCH v5 23/60] target/riscv: vector single-width saturating add and subtract
,
Richard Henderson
,
03:52
Re: [PATCH v5 22/60] target/riscv: vector integer merge and move instructions
,
Richard Henderson
,
03:35
Re: [PATCH v5 21/60] target/riscv: vector widening integer multiply-add instructions
,
Richard Henderson
,
03:35
Re: [PATCH v5 20/60] target/riscv: vector single-width integer multiply-add instructions
,
Richard Henderson
,
03:35
Re: [PATCH v5 19/60] target/riscv: vector widening integer multiply instructions
,
Richard Henderson
,
03:06
Re: [PATCH v5 17/60] target/riscv: vector single-width integer multiply instructions
,
LIU Zhiwei
,
03:03
Re: [PATCH v5 18/60] target/riscv: vector integer divide instructions
,
Richard Henderson
,
02:58
Re: [PATCH v5 17/60] target/riscv: vector single-width integer multiply instructions
,
Richard Henderson
,
02:52
Re: [PATCH v5 16/60] target/riscv: vector integer min/max instructions
,
Richard Henderson
,
02:40
Re: [PATCH v5 15/60] target/riscv: vector integer comparison instructions
,
Richard Henderson
,
02:33
Re: [PATCH v5 11/60] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
,
LIU Zhiwei
,
02:32
Re: [PATCH v5 11/60] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
,
Richard Henderson
,
02:16
Re: [PATCH v5 14/60] target/riscv: vector narrowing integer right shift instructions
,
Richard Henderson
,
02:10
Re: [PATCH v5 11/60] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
,
LIU Zhiwei
,
02:08
Re: [PATCH v5 13/60] target/riscv: vector single-width bit shift instructions
,
Richard Henderson
,
02:08
Re: [PATCH v5 12/60] target/riscv: vector bitwise logical instructions
,
Richard Henderson
,
02:00
Re: [PATCH v5 11/60] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
,
Richard Henderson
,
01:59
Re: [PATCH v5 10/60] target/riscv: vector widening integer add and subtract
,
Richard Henderson
,
01:32
Re: [PATCH v5 09/60] target/riscv: vector single-width integer add and subtract
,
Richard Henderson
,
01:25
Re: [PATCH v5 08/60] target/riscv: add vector amo operations
,
LIU Zhiwei
,
01:07
Re: [PATCH v5 08/60] target/riscv: add vector amo operations
,
Richard Henderson
,
00:28
March 13, 2020
Re: [PATCH v2 2/2] target/riscv: Add a sifive-e34 cpu type
,
Bin Meng
,
22:47
Re: [PATCH v5 07/60] target/riscv: add fault-only-first unit stride load
,
Richard Henderson
,
21:50
Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions
,
LIU Zhiwei
,
21:49
Re: [PATCH v5 06/60] target/riscv: add vector index load and store instructions
,
Richard Henderson
,
21:49
Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions
,
Richard Henderson
,
21:36
Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions
,
Richard Henderson
,
21:26
Re: [PATCH v5 04/60] target/riscv: add vector configure instruction
,
Richard Henderson
,
21:14
Re: [PATCH v5 03/60] target/riscv: support vector extension csr
,
Richard Henderson
,
21:11
Re: [PATCH v5 08/60] target/riscv: add vector amo operations
,
LIU Zhiwei
,
20:36
Re: [PATCH v8 0/4] linux-user: generate syscall_nr.sh for RISC-V
,
no-reply
,
20:19
[PATCH v8 4/4] linux-user/riscv: Update the syscall_nr's to the 5.5 kernel
,
Alistair Francis
,
20:04
[PATCH v8 3/4] linux-user: Support futex_time64
,
Alistair Francis
,
20:04
[PATCH v8 1/4] linux-user: Protect more syscalls
,
Alistair Francis
,
20:04
[PATCH v8 2/4] linux-user/syscall: Add support for clock_gettime64/clock_settime64
,
Alistair Francis
,
20:04
[PATCH v8 0/4] linux-user: generate syscall_nr.sh for RISC-V
,
Alistair Francis
,
20:04
Re: [PATCH v5 08/60] target/riscv: add vector amo operations
,
Alistair Francis
,
20:03
Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions
,
Alistair Francis
,
19:39
Re: [PATCH v5 07/60] target/riscv: add fault-only-first unit stride load
,
LIU Zhiwei
,
18:42
Re: [PATCH 01/14] Makefile: Only build virtiofsd if system-mode is enabled
,
Laurent Vivier
,
18:28
Re: [PATCH v1 1/1] target/riscv: Don't set write permissions on dirty PTEs
,
Alistair Francis
,
18:27
Re: [PATCH v5 07/60] target/riscv: add fault-only-first unit stride load
,
Alistair Francis
,
18:25
Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions
,
LIU Zhiwei
,
18:18
Re: [PATCH v7 3/4] linux-user: Support futex_time64
,
Laurent Vivier
,
18:18
Re: [PATCH v7 3/4] linux-user: Support futex_time64
,
Alistair Francis
,
18:13
Re: [PATCH v7 3/4] linux-user: Support futex_time64
,
Alistair Francis
,
18:12
Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions
,
Alistair Francis
,
18:06
Re: [PATCH v5 60/60] target/riscv: configure and turn on vector extension from command line
,
LIU Zhiwei
,
17:52
Re: [PATCH v7 4/4] linux-user/riscv: Update the syscall_nr's to the 5.5 kernel
,
Laurent Vivier
,
17:50
Re: [PATCH v7 2/4] linux-user/syscall: Add support for clock_gettime64/clock_settime64
,
Laurent Vivier
,
17:48
Re: [PATCH v7 1/4] linux-user: Protect more syscalls
,
Laurent Vivier
,
17:47
Re: [PATCH v5 60/60] target/riscv: configure and turn on vector extension from command line
,
Alistair Francis
,
17:42
Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions
,
LIU Zhiwei
,
17:33
Re: [PATCH v5 06/60] target/riscv: add vector index load and store instructions
,
Alistair Francis
,
17:22
Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions
,
Alistair Francis
,
16:39
Re: [PATCH 10/14] arch_init: Remove unused 'qapi-commands-misc.h' include
,
Alistair Francis
,
16:03
Re: [PATCH 09/14] exec: Drop redundant #ifdeffery
,
Alistair Francis
,
16:02
Re: [PATCH 07/14] target/riscv/cpu: Restrict CPU migration to system-mode
,
Alistair Francis
,
16:01
Re: [PATCH v2 2/2] target/riscv: Add a sifive-e34 cpu type
,
Alistair Francis
,
16:01
Re: [PATCH v2 1/2] riscv: sifive_e: Support changing CPU type
,
Philippe Mathieu-Daudé
,
15:46
Re: [PATCH 03/14] tests/Makefile: Only display TCG-related tests when TCG is available
,
Alistair Francis
,
15:46
[PATCH v2 0/2] Support different CPU types for the sifive_e machine
,
Corey Wharton
,
15:35
[PATCH v2 2/2] target/riscv: Add a sifive-e34 cpu type
,
Corey Wharton
,
15:35
[PATCH v2 1/2] riscv: sifive_e: Support changing CPU type
,
Corey Wharton
,
15:35
[PATCH 14/14] hw/core: Restrict CpuClass::get_crash_info() to system-mode
,
Philippe Mathieu-Daudé
,
14:38
[PATCH 13/14] target/s390x: Restrict CpuClass::get_crash_info() to system-mode
,
Philippe Mathieu-Daudé
,
14:38
[PATCH 12/14] target/i386: Restrict CpuClass::get_crash_info() to system-mode
,
Philippe Mathieu-Daudé
,
14:38
[PATCH 11/14] target: Restrict write_elfXX_note() handlers to system-mode
,
Philippe Mathieu-Daudé
,
14:37
[PATCH 10/14] arch_init: Remove unused 'qapi-commands-misc.h' include
,
Philippe Mathieu-Daudé
,
14:37
[PATCH 09/14] exec: Drop redundant #ifdeffery
,
Philippe Mathieu-Daudé
,
14:37
[PATCH 08/14] exec: Assert CPU migration is not used on user-only build
,
Philippe Mathieu-Daudé
,
14:37
[PATCH 07/14] target/riscv/cpu: Restrict CPU migration to system-mode
,
Philippe Mathieu-Daudé
,
14:37
[PATCH 06/14] util/Makefile: Reduce the user-mode object list
,
Philippe Mathieu-Daudé
,
14:37
[PATCH 05/14] stubs/Makefile: Reduce the user-mode object list
,
Philippe Mathieu-Daudé
,
14:37
[PATCH 04/14] tests/Makefile: Restrict some softmmu-only tests
,
Philippe Mathieu-Daudé
,
14:37
[PATCH 03/14] tests/Makefile: Only display TCG-related tests when TCG is available
,
Philippe Mathieu-Daudé
,
14:37
[PATCH 02/14] configure: Avoid building TCG when not needed
,
Philippe Mathieu-Daudé
,
14:37
[PATCH 01/14] Makefile: Only build virtiofsd if system-mode is enabled
,
Philippe Mathieu-Daudé
,
14:37
[PATCH 00/14] user-mode: Prune build dependencies (part 1)
,
Philippe Mathieu-Daudé
,
14:37
Re: [PATCH 1/2] riscv: sifive_e: Support changing CPU type
,
Alistair Francis
,
14:32
Re: [PATCH 2/2] target/riscv: Add a sifive-e34 cpu type
,
Bin Meng
,
10:43
Re: [PATCH 1/2] riscv: sifive_e: Support changing CPU type
,
Bin Meng
,
10:39
Re: [PATCH v7 3/4] linux-user: Support futex_time64
,
Laurent Vivier
,
04:14
RE: [PATCH RFC 0/9] Add riscv64 kvm accel support
,
Jiangyifei
,
03:02
Re: [PATCH RFC 0/9] Add riscv64 kvm accel support
,
Anup Patel
,
02:00
Re: [PATCH v1 1/1] target/riscv: Don't set write permissions on dirty PTEs
,
Richard Henderson
,
01:26
March 12, 2020
[PATCH RFC 0/9] Add riscv64 kvm accel support
,
Yifei Jiang
,
23:52
[PATCH RFC 5/9] target/riscv: Implement kvm_arch_put_registers
,
Yifei Jiang
,
23:52
[PATCH RFC 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
,
Yifei Jiang
,
23:52
[PATCH RFC 1/9] linux-header: Update linux/kvm.h
,
Yifei Jiang
,
23:52
[PATCH RFC 9/9] target/riscv: add host riscv64 cpu type
,
Yifei Jiang
,
23:51
[PATCH RFC 4/9] target/riscv: Implement kvm_arch_get_registers
,
Yifei Jiang
,
23:51
[PATCH RFC 6/9] target/riscv: Support start kernel directly by KVM
,
Yifei Jiang
,
23:51
[PATCH RFC 7/9] hw/riscv: PLIC update external interrupt by KVM when kvm enabled
,
Yifei Jiang
,
23:51
[PATCH RFC 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit
,
Yifei Jiang
,
23:51
[PATCH RFC 3/9] target/riscv: Implement function kvm_arch_init_vcpu
,
Yifei Jiang
,
23:51
Re: [PATCH v7 0/4] linux-user: generate syscall_nr.sh for RISC-V
,
no-reply
,
21:47
[PATCH 2/2] target/riscv: Add a sifive-e34 cpu type
,
Corey Wharton
,
20:56
[PATCH 1/2] riscv: sifive_e: Support changing CPU type
,
Corey Wharton
,
20:56
[PATCH 0/2] Support different CPU types for the sifive_e machine
,
Corey Wharton
,
20:55
[PATCH 1/2] riscv: sifive_e: Support changing CPU type
,
Corey Wharton
,
20:50
[PATCH 0/2] Support different CPU types for the sifive_e machine
,
Corey Wharton
,
20:50
[PATCH 2/2] target/riscv: Add a sifive-e34 cpu type
,
Corey Wharton
,
20:50
Re: [PATCH v5 00/60] target/riscv: support vector extension v0.7.1
,
no-reply
,
20:42
[PATCH v7 4/4] linux-user/riscv: Update the syscall_nr's to the 5.5 kernel
,
Alistair Francis
,
18:21
[PATCH v7 3/4] linux-user: Support futex_time64
,
Alistair Francis
,
18:21
[PATCH v7 1/4] linux-user: Protect more syscalls
,
Alistair Francis
,
18:21
[PATCH v7 2/4] linux-user/syscall: Add support for clock_gettime64/clock_settime64
,
Alistair Francis
,
18:21
[PATCH v7 0/4] linux-user: generate syscall_nr.sh for RISC-V
,
Alistair Francis
,
18:21
Re: [PATCH v1 1/1] target/riscv: Don't set write permissions on dirty PTEs
,
Alistair Francis
,
18:18
Re: [PATCH v5 04/60] target/riscv: add vector configure instruction
,
Alistair Francis
,
18:15
Re: [PATCH v5 04/60] target/riscv: add vector configure instruction
,
LIU Zhiwei
,
18:00
Re: [PATCH v5 04/60] target/riscv: add vector configure instruction
,
Alistair Francis
,
17:31
Re: [PATCH v5 03/60] target/riscv: support vector extension csr
,
Alistair Francis
,
17:02
[PATCH v5 60/60] target/riscv: configure and turn on vector extension from command line
,
LIU Zhiwei
,
13:00
[PATCH v5 59/60] target/riscv: vector compress instruction
,
LIU Zhiwei
,
12:58
[PATCH v5 58/60] target/riscv: vector register gather instruction
,
LIU Zhiwei
,
12:56
[PATCH v5 57/60] target/riscv: vector slide instructions
,
LIU Zhiwei
,
12:54
[PATCH v5 56/60] target/riscv: floating-point scalar move instructions
,
LIU Zhiwei
,
12:52
[PATCH v5 55/60] target/riscv: integer scalar move instruction
,
LIU Zhiwei
,
12:50
[PATCH v5 54/60] target/riscv: integer extract instruction
,
LIU Zhiwei
,
12:48
[PATCH v5 53/60] target/riscv: vector element index instruction
,
LIU Zhiwei
,
12:46
[PATCH v5 52/60] target/riscv: vector iota instruction
,
LIU Zhiwei
,
12:44
[PATCH v5 51/60] target/riscv: set-X-first mask bit
,
LIU Zhiwei
,
12:42
[PATCH v5 50/60] target/riscv: vmfirst find-first-set mask bit
,
LIU Zhiwei
,
12:40
[PATCH v5 49/60] target/riscv: vector mask population count vmpopc
,
LIU Zhiwei
,
12:38
[PATCH v5 48/60] target/riscv: vector mask-register logical instructions
,
LIU Zhiwei
,
12:36
[PATCH v5 47/60] target/riscv: vector widening floating-point reduction instructions
,
LIU Zhiwei
,
12:34
[PATCH v5 46/60] target/riscv: vector single-width floating-point reduction instructions
,
LIU Zhiwei
,
12:32
[PATCH v5 45/60] target/riscv: vector wideing integer reduction instructions
,
LIU Zhiwei
,
12:30
[PATCH v5 44/60] target/riscv: vector single-width integer reduction instructions
,
LIU Zhiwei
,
12:28
[PATCH v5 43/60] target/riscv: narrowing floating-point/integer type-convert instructions
,
LIU Zhiwei
,
12:26
[PATCH v5 42/60] target/riscv: widening floating-point/integer type-convert instructions
,
LIU Zhiwei
,
12:24
[PATCH v5 41/60] target/riscv: vector floating-point/integer type-convert instructions
,
LIU Zhiwei
,
12:22
[PATCH v5 40/60] target/riscv: vector floating-point merge instructions
,
LIU Zhiwei
,
12:20
[PATCH v5 39/60] target/riscv: vector floating-point classify instructions
,
LIU Zhiwei
,
12:18
[PATCH v5 38/60] target/riscv: vector floating-point compare instructions
,
LIU Zhiwei
,
12:16
[PATCH v5 37/60] target/riscv: vector floating-point sign-injection instructions
,
LIU Zhiwei
,
12:14
[PATCH v5 36/60] target/riscv: vector floating-point min/max instructions
,
LIU Zhiwei
,
12:12
[PATCH v5 35/60] target/riscv: vector floating-point square-root instruction
,
LIU Zhiwei
,
12:10
[PATCH v5 34/60] target/riscv: vector widening floating-point fused multiply-add instructions
,
LIU Zhiwei
,
12:08
[PATCH v5 33/60] target/riscv: vector single-width floating-point fused multiply-add instructions
,
LIU Zhiwei
,
12:06
[PATCH v5 32/60] target/riscv: vector widening floating-point multiply
,
LIU Zhiwei
,
12:04
[PATCH v5 31/60] target/riscv: vector single-width floating-point multiply/divide instructions
,
LIU Zhiwei
,
12:02
[PATCH v5 30/60] target/riscv: vector widening floating-point add/subtract instructions
,
LIU Zhiwei
,
12:00
[PATCH v5 29/60] target/riscv: vector single-width floating-point add/subtract instructions
,
LIU Zhiwei
,
11:58
[PATCH v5 28/60] target/riscv: vector narrowing fixed-point clip instructions
,
LIU Zhiwei
,
11:56
[PATCH v5 27/60] target/riscv: vector single-width scaling shift instructions
,
LIU Zhiwei
,
11:54
[PATCH v5 26/60] target/riscv: vector widening saturating scaled multiply-add
,
LIU Zhiwei
,
11:51
[PATCH v5 25/60] target/riscv: vector single-width fractional multiply with rounding and saturation
,
LIU Zhiwei
,
11:49
[PATCH v5 24/60] target/riscv: vector single-width averaging add and subtract
,
LIU Zhiwei
,
11:47
[PATCH v5 23/60] target/riscv: vector single-width saturating add and subtract
,
LIU Zhiwei
,
11:46
[PATCH v5 22/60] target/riscv: vector integer merge and move instructions
,
LIU Zhiwei
,
11:44
[PATCH v5 21/60] target/riscv: vector widening integer multiply-add instructions
,
LIU Zhiwei
,
11:41
[PATCH v5 20/60] target/riscv: vector single-width integer multiply-add instructions
,
LIU Zhiwei
,
11:39
[PATCH v5 19/60] target/riscv: vector widening integer multiply instructions
,
LIU Zhiwei
,
11:37
[PATCH v5 18/60] target/riscv: vector integer divide instructions
,
LIU Zhiwei
,
11:35
[PATCH v5 17/60] target/riscv: vector single-width integer multiply instructions
,
LIU Zhiwei
,
11:33
[PATCH v5 16/60] target/riscv: vector integer min/max instructions
,
LIU Zhiwei
,
11:31
[PATCH v5 15/60] target/riscv: vector integer comparison instructions
,
LIU Zhiwei
,
11:29
[PATCH v5 14/60] target/riscv: vector narrowing integer right shift instructions
,
LIU Zhiwei
,
11:27
[PATCH v5 13/60] target/riscv: vector single-width bit shift instructions
,
LIU Zhiwei
,
11:25
[PATCH v5 12/60] target/riscv: vector bitwise logical instructions
,
LIU Zhiwei
,
11:23
[PATCH v5 11/60] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
,
LIU Zhiwei
,
11:21
[PATCH v5 10/60] target/riscv: vector widening integer add and subtract
,
LIU Zhiwei
,
11:19
[PATCH v5 09/60] target/riscv: vector single-width integer add and subtract
,
LIU Zhiwei
,
11:17
[PATCH v5 08/60] target/riscv: add vector amo operations
,
LIU Zhiwei
,
11:15
[PATCH v5 07/60] target/riscv: add fault-only-first unit stride load
,
LIU Zhiwei
,
11:13
[PATCH v5 06/60] target/riscv: add vector index load and store instructions
,
LIU Zhiwei
,
11:11
[PATCH v5 05/60] target/riscv: add vector stride load and store instructions
,
LIU Zhiwei
,
11:09
[PATCH v5 04/60] target/riscv: add vector configure instruction
,
LIU Zhiwei
,
11:07
[PATCH v5 03/60] target/riscv: support vector extension csr
,
LIU Zhiwei
,
11:05
[PATCH v5 02/60] target/riscv: implementation-defined constant parameters
,
LIU Zhiwei
,
11:03
[PATCH v5 01/60] target/riscv: add vector extension field in CPURISCVState
,
LIU Zhiwei
,
11:01
[PATCH v5 00/60] target/riscv: support vector extension v0.7.1
,
LIU Zhiwei
,
10:59
March 11, 2020
[PATCH v4 33/60] target/riscv: vector single-width floating-point fused multiply-add instructions
,
LIU Zhiwei
,
01:11
[PATCH v4 35/60] target/riscv: vector floating-point square-root instruction
,
LIU Zhiwei
,
01:11
[PATCH v4 30/60] target/riscv: vector widening floating-point add/subtract instructions
,
LIU Zhiwei
,
01:11
[PATCH v4 34/60] target/riscv: vector widening floating-point fused multiply-add instructions
,
LIU Zhiwei
,
01:11
[PATCH v4 31/60] target/riscv: vector single-width floating-point multiply/divide instructions
,
LIU Zhiwei
,
01:11
[PATCH v4 32/60] target/riscv: vector widening floating-point multiply
,
LIU Zhiwei
,
01:11
[PATCH v4 29/60] target/riscv: vector single-width floating-point add/subtract instructions
,
LIU Zhiwei
,
01:10
[PATCH v4 28/60] target/riscv: vector narrowing fixed-point clip instructions
,
LIU Zhiwei
,
01:10
[PATCH v4 27/60] target/riscv: vector single-width scaling shift instructions
,
LIU Zhiwei
,
01:10
[PATCH v4 23/60] target/riscv: vector single-width saturating add and subtract
,
LIU Zhiwei
,
01:10
[PATCH v4 26/60] target/riscv: vector widening saturating scaled multiply-add
,
LIU Zhiwei
,
01:10
[PATCH v4 24/60] target/riscv: vector single-width averaging add and subtract
,
LIU Zhiwei
,
01:10
[PATCH v4 25/60] target/riscv: vector single-width fractional multiply with rounding and saturation
,
LIU Zhiwei
,
01:10
[PATCH v4 21/60] target/riscv: vector widening integer multiply-add instructions
,
LIU Zhiwei
,
01:10
[PATCH v4 22/60] target/riscv: vector integer merge and move instructions
,
LIU Zhiwei
,
01:10
[PATCH v4 20/60] target/riscv: vector single-width integer multiply-add instructions
,
LIU Zhiwei
,
01:10
[PATCH v4 18/60] target/riscv: vector integer divide instructions
,
LIU Zhiwei
,
01:09
[PATCH v4 19/60] target/riscv: vector widening integer multiply instructions
,
LIU Zhiwei
,
01:09
[PATCH v4 16/60] target/riscv: vector integer min/max instructions
,
LIU Zhiwei
,
01:09
[PATCH v4 15/60] target/riscv: vector integer comparison instructions
,
LIU Zhiwei
,
01:09
[PATCH v4 13/60] target/riscv: vector single-width bit shift instructions
,
LIU Zhiwei
,
01:09
[PATCH v4 11/60] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
,
LIU Zhiwei
,
01:09
[PATCH v4 10/60] target/riscv: vector widening integer add and subtract
,
LIU Zhiwei
,
01:09
[PATCH v4 12/60] target/riscv: vector bitwise logical instructions
,
LIU Zhiwei
,
01:09
[PATCH v4 17/60] target/riscv: vector single-width integer multiply instructions
,
LIU Zhiwei
,
01:09
[PATCH v4 14/60] target/riscv: vector narrowing integer right shift instructions
,
LIU Zhiwei
,
01:09
[PATCH v4 05/60] target/riscv: add vector stride load and store instructions
,
LIU Zhiwei
,
01:08
[PATCH v4 08/60] target/riscv: add vector amo operations
,
LIU Zhiwei
,
01:07
[PATCH v4 04/60] target/riscv: add vector configure instruction
,
LIU Zhiwei
,
01:07
[PATCH v4 09/60] target/riscv: vector single-width integer add and subtract
,
LIU Zhiwei
,
01:07
[PATCH v4 06/60] target/riscv: add vector index load and store instructions
,
LIU Zhiwei
,
01:07
[PATCH v4 00/60] target/riscv: support vector extension v0.7.1
,
LIU Zhiwei
,
01:07
[PATCH v4 02/60] target/riscv: implementation-defined constant parameters
,
LIU Zhiwei
,
01:07
[PATCH v4 01/60] target/riscv: add vector extension field in CPURISCVState
,
LIU Zhiwei
,
01:07
[PATCH v4 07/60] target/riscv: add fault-only-first unit stride load
,
LIU Zhiwei
,
01:07
[PATCH v4 03/60] target/riscv: support vector extension csr
,
LIU Zhiwei
,
01:07
March 09, 2020
Re: [PATCH] hw/riscv: Generate correct "mmu-type" for 32-bit machines
,
Alistair Francis
,
13:22
[PATCH v3 35/60] target/riscv: vector floating-point square-root instruction
,
LIU Zhiwei
,
08:16
[PATCH v3 11/60] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
,
LIU Zhiwei
,
08:16
[PATCH v3 17/60] target/riscv: vector single-width integer multiply instructions
,
LIU Zhiwei
,
08:16
[PATCH v3 33/60] target/riscv: vector single-width floating-point fused multiply-add instructions
,
LIU Zhiwei
,
08:16
[PATCH v3 32/60] target/riscv: vector widening floating-point multiply
,
LIU Zhiwei
,
08:16
[PATCH v3 23/60] target/riscv: vector single-width saturating add and subtract
,
LIU Zhiwei
,
08:16
[PATCH v3 09/60] target/riscv: vector single-width integer add and subtract
,
LIU Zhiwei
,
08:16
[PATCH v3 24/60] target/riscv: vector single-width averaging add and subtract
,
LIU Zhiwei
,
08:16
[PATCH v3 22/60] target/riscv: vector integer merge and move instructions
,
LIU Zhiwei
,
08:16
[PATCH v3 27/60] target/riscv: vector single-width scaling shift instructions
,
LIU Zhiwei
,
08:16
[PATCH v3 20/60] target/riscv: vector single-width integer multiply-add instructions
,
LIU Zhiwei
,
08:16
[PATCH v3 30/60] target/riscv: vector widening floating-point add/subtract instructions
,
LIU Zhiwei
,
08:16
[PATCH v3 37/60] target/riscv: vector floating-point sign-injection instructions
,
LIU Zhiwei
,
08:16
[PATCH v3 26/60] target/riscv: vector widening saturating scaled multiply-add
,
LIU Zhiwei
,
08:16
[PATCH v3 28/60] target/riscv: vector narrowing fixed-point clip instructions
,
LIU Zhiwei
,
08:16
[PATCH v3 19/60] target/riscv: vector widening integer multiply instructions
,
LIU Zhiwei
,
08:16
[PATCH v3 12/60] target/riscv: vector bitwise logical instructions
,
LIU Zhiwei
,
08:16
[PATCH v3 21/60] target/riscv: vector widening integer multiply-add instructions
,
LIU Zhiwei
,
08:16
[PATCH v3 14/60] target/riscv: vector narrowing integer right shift instructions
,
LIU Zhiwei
,
08:15
[PATCH v3 25/60] target/riscv: vector single-width fractional multiply with rounding and saturation
,
LIU Zhiwei
,
08:15
[PATCH v3 31/60] target/riscv: vector single-width floating-point multiply/divide instructions
,
LIU Zhiwei
,
08:15
[PATCH v3 29/60] target/riscv: vector single-width floating-point add/subtract instructions
,
LIU Zhiwei
,
08:15
[PATCH v3 05/60] target/riscv: add vector stride load and store instructions
,
LIU Zhiwei
,
08:15
[PATCH v3 18/60] target/riscv: vector integer divide instructions
,
LIU Zhiwei
,
08:15
[PATCH v3 08/60] target/riscv: add vector amo operations
,
LIU Zhiwei
,
08:15
[PATCH v3 10/60] target/riscv: vector widening integer add and subtract
,
LIU Zhiwei
,
08:15
[PATCH v3 06/60] target/riscv: add vector index load and store instructions
,
LIU Zhiwei
,
08:15
[PATCH v3 04/60] target/riscv: add vector configure instruction
,
LIU Zhiwei
,
08:15
[PATCH v3 07/60] target/riscv: add fault-only-first unit stride load
,
LIU Zhiwei
,
08:15
[PATCH v3 01/60] target/riscv: add vector extension field in CPURISCVState
,
LIU Zhiwei
,
08:15
[PATCH v3 03/60] target/riscv: support vector extension csr
,
LIU Zhiwei
,
08:15
[PATCH v3 00/60] target/riscv: support vector extension v0.7.1
,
LIU Zhiwei
,
08:15
[PATCH v3 02/60] target/riscv: implementation-defined constant parameters
,
LIU Zhiwei
,
08:15
[PATCH v3 43/60] target/riscv: narrowing floating-point/integer type-convert instructions
,
LIU Zhiwei
,
08:14
[PATCH v3 50/60] target/riscv: vmfirst find-first-set mask bit
,
LIU Zhiwei
,
08:09
[PATCH v3 49/60] target/riscv: vector mask population count vmpopc
,
LIU Zhiwei
,
08:09
[PATCH v3 48/60] target/riscv: vector mask-register logical instructions
,
LIU Zhiwei
,
08:09
[PATCH v3 47/60] target/riscv: vector widening floating-point reduction instructions
,
LIU Zhiwei
,
08:08
[PATCH v3 46/60] target/riscv: vector single-width floating-point reduction instructions
,
LIU Zhiwei
,
08:08
[PATCH v3 45/60] target/riscv: vector wideing integer reduction instructions
,
LIU Zhiwei
,
08:08
[PATCH v3 44/60] target/riscv: vector single-width integer reduction instructions
,
LIU Zhiwei
,
08:08
[PATCH v3 16/60] target/riscv: vector integer min/max instructions
,
LIU Zhiwei
,
08:07
Re: [PATCH] cpu: Use DeviceClass reset instead of a special CPUClass reset
,
Christian Borntraeger
,
07:02
[PATCH v3 03/60] target/riscv: support vector extension csr
,
LIU Zhiwei
,
05:21
[PATCH v3 02/60] target/riscv: implementation-defined constant parameters
,
LIU Zhiwei
,
05:21
[PATCH v3 01/60] target/riscv: add vector extension field in CPURISCVState
,
LIU Zhiwei
,
05:20
[PATCH v3 00/60] target/riscv: support vector extension v0.7.1
,
LIU Zhiwei
,
05:20
[PATCH v3 33/60] target/riscv: vector single-width floating-point fused multiply-add instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 43/60] target/riscv: narrowing floating-point/integer type-convert instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 29/60] target/riscv: vector single-width floating-point add/subtract instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 48/60] target/riscv: vector mask-register logical instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 35/60] target/riscv: vector floating-point square-root instruction
,
LIU Zhiwei
,
04:22
[PATCH v3 32/60] target/riscv: vector widening floating-point multiply
,
LIU Zhiwei
,
04:22
[PATCH v3 45/60] target/riscv: vector wideing integer reduction instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 40/60] target/riscv: vector floating-point merge instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 41/60] target/riscv: vector floating-point/integer type-convert instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 26/60] target/riscv: vector widening saturating scaled multiply-add
,
LIU Zhiwei
,
04:22
[PATCH v3 38/60] target/riscv: vector floating-point compare instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 15/60] target/riscv: vector integer comparison instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 30/60] target/riscv: vector widening floating-point add/subtract instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 28/60] target/riscv: vector narrowing fixed-point clip instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 39/60] target/riscv: vector floating-point classify instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 37/60] target/riscv: vector floating-point sign-injection instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 42/60] target/riscv: widening floating-point/integer type-convert instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 36/60] target/riscv: vector floating-point min/max instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 13/60] target/riscv: vector single-width bit shift instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 24/60] target/riscv: vector single-width averaging add and subtract
,
LIU Zhiwei
,
04:22
[PATCH v3 34/60] target/riscv: vector widening floating-point fused multiply-add instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 23/60] target/riscv: vector single-width saturating add and subtract
,
LIU Zhiwei
,
04:22
[PATCH v3 19/60] target/riscv: vector widening integer multiply instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 31/60] target/riscv: vector single-width floating-point multiply/divide instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 11/60] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 22/60] target/riscv: vector integer merge and move instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 27/60] target/riscv: vector single-width scaling shift instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 18/60] target/riscv: vector integer divide instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 25/60] target/riscv: vector single-width fractional multiply with rounding and saturation
,
LIU Zhiwei
,
04:22
[PATCH v3 17/60] target/riscv: vector single-width integer multiply instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 20/60] target/riscv: vector single-width integer multiply-add instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 14/60] target/riscv: vector narrowing integer right shift instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 21/60] target/riscv: vector widening integer multiply-add instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 12/60] target/riscv: vector bitwise logical instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 08/60] target/riscv: add vector amo operations
,
LIU Zhiwei
,
04:22
[PATCH v3 05/60] target/riscv: add vector stride load and store instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 10/60] target/riscv: vector widening integer add and subtract
,
LIU Zhiwei
,
04:22
[PATCH v3 09/60] target/riscv: vector single-width integer add and subtract
,
LIU Zhiwei
,
04:22
[PATCH v3 04/60] target/riscv: add vector configure instruction
,
LIU Zhiwei
,
04:22
[PATCH v3 06/60] target/riscv: add vector index load and store instructions
,
LIU Zhiwei
,
04:22
[PATCH v3 07/60] target/riscv: add fault-only-first unit stride load
,
LIU Zhiwei
,
04:22
[PATCH v3 03/60] target/riscv: support vector extension csr
,
LIU Zhiwei
,
04:22
[PATCH v3 00/60] target/riscv: support vector extension v0.7.1
,
LIU Zhiwei
,
04:22
[PATCH v3 02/60] target/riscv: implementation-defined constant parameters
,
LIU Zhiwei
,
04:22
[PATCH v3 01/60] target/riscv: add vector extension field in CPURISCVState
,
LIU Zhiwei
,
04:21
March 08, 2020
Re: [PATCH v6 3/4] linux-user: Support futex_time64
,
Laurent Vivier
,
14:17
March 07, 2020
Re: [PATCH] riscv: Add semihosting support [v4]
,
Keith Packard
,
14:44
Re: [PATCH v4 1/5] target/riscv: add vector unit stride load and store instructions
,
Richard Henderson
,
12:44
Re: [PATCH] hw/riscv: Generate correct "mmu-type" for 32-bit machines
,
no-reply
,
08:15
[PATCH] hw/riscv: Generate correct "mmu-type" for 32-bit machines
,
Bin Meng
,
07:48
March 06, 2020
Re: [PATCH v4 1/5] target/riscv: add vector unit stride load and store instructions
,
LIU Zhiwei
,
23:37
Re: [PATCH v4 2/5] target/riscv: add vector stride load and store instructions
,
LIU Zhiwei
,
23:30
Re: [PATCH v3 1/3] riscv/sifive_u: Fix up file ordering
,
Bin Meng
,
20:14
[PATCH v3 3/3] riscv/sifive_u: Add a serial property to the sifive_u machine
,
Alistair Francis
,
16:44
[PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u
,
Alistair Francis
,
16:44
[PATCH v3 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC
,
Alistair Francis
,
16:44
[PATCH v3 1/3] riscv/sifive_u: Fix up file ordering
,
Alistair Francis
,
16:44
Re: [PATCH v6 0/4] linux-user: generate syscall_nr.sh for RISC-V
,
no-reply
,
16:35
Re: [PATCH v6 1/4] linux-user: Protect more syscalls
,
Laurent Vivier
,
15:56
Re: [PATCH v1 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC
,
Alistair Francis
,
14:51
[PATCH v6 4/4] linux-user/riscv: Update the syscall_nr's to the 5.5 kernel
,
Alistair Francis
,
13:32
[PATCH v6 1/4] linux-user: Protect more syscalls
,
Alistair Francis
,
13:32
[PATCH v6 3/4] linux-user: Support futex_time64
,
Alistair Francis
,
13:32
[PATCH v6 0/4] linux-user: generate syscall_nr.sh for RISC-V
,
Alistair Francis
,
13:32
[PATCH v6 2/4] linux-user/syscall: Add support for clock_gettime64/clock_settime64
,
Alistair Francis
,
13:32
Re: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding.
,
Palmer Dabbelt
,
12:31
Re: [PULL] A single RISC-V fixup
,
Peter Maydell
,
04:54
March 05, 2020
Re: [PATCH v1 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC
,
Bin Meng
,
19:09
Re: [PATCH v2 0/4] riscv: Upgrade OpenSBI to v0.6 and add 32-bit sifive_u bios image
,
Palmer Dabbelt
,
19:06
Re: [PATCH v2 4/4] gitlab-ci.yml: Add jobs to build OpenSBI firmware binaries
,
Palmer Dabbelt
,
19:02
Re: [PATCH v1 1/1] target/riscv: Correctly implement TSR trap
,
Palmer Dabbelt
,
16:48
Re: [PATCH v5 1/3] linux-user: Protect more syscalls
,
Laurent Vivier
,
15:52
Re: [PATCH v5 3/3] linux-user/riscv: Update the syscall_nr's to the 5.5 kernel
,
Laurent Vivier
,
15:15
Re: [PATCH v5 2/3] linux-user/syscall: Add support for clock_gettime64/clock_settime64
,
Laurent Vivier
,
15:15
Re: [PATCH] RISC-V: Add a missing "," in riscv_excp_names
,
Palmer Dabbelt
,
15:06
[PULL] RISC-V: Add a missing "," in riscv_excp_names
,
Palmer Dabbelt
,
15:06
[PULL] A single RISC-V fixup
,
Palmer Dabbelt
,
15:06
[PATCH v5 3/3] linux-user/riscv: Update the syscall_nr's to the 5.5 kernel
,
Alistair Francis
,
14:56
[PATCH v5 1/3] linux-user: Protect more syscalls
,
Alistair Francis
,
14:56
[PATCH v5 0/3] linux-user: generate syscall_nr.sh for RISC-V
,
Alistair Francis
,
14:56
[PATCH v5 2/3] linux-user/syscall: Add support for clock_gettime64/clock_settime64
,
Alistair Francis
,
14:56
Re: [PATCH] RISC-V: Add a missing "," in riscv_excp_names
,
Philippe Mathieu-Daudé
,
12:20
Re: [PATCH] RISC-V: Add a missing "," in riscv_excp_names
,
Philippe Mathieu-Daudé
,
12:19
Re: [PULL 04/38] target/riscv: Add support for the new execption numbers
,
Alistair Francis
,
11:54
Re: [PATCH v1 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC
,
Alistair Francis
,
11:53
Re: [PULL 04/38] target/riscv: Add support for the new execption numbers
,
Palmer Dabbelt
,
11:51
[PATCH] RISC-V: Add a missing "," in riscv_excp_names
,
Palmer Dabbelt
,
11:51
Re: [PULL 04/38] target/riscv: Add support for the new execption numbers
,
Peter Maydell
,
11:44
Re: [PATCH v1 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC
,
Bin Meng
,
04:31
Re: [PATCH v2 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC
,
Bin Meng
,
04:26
March 04, 2020
Re: [PATCH v1 1/3] riscv/sifive_u: Fix up file ordering
,
Alistair Francis
,
19:02
Re: [PATCH v2 0/3] hw/riscv: Add a serial property to the sifive_u machine
,
no-reply
,
18:53
Re: [PATCH v2] riscv: sifive_u: Add a "serial" property for board serial number
,
Alistair Francis
,
18:15
Re: [PATCH v1 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC
,
Alistair Francis
,
18:14
[PATCH v2 3/3] riscv/sifive_u: Add a serial property to the sifive_u machine
,
Alistair Francis
,
18:10
[PATCH v2 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC
,
Alistair Francis
,
18:10
[PATCH v2 0/3] hw/riscv: Add a serial property to the sifive_u machine
,
Alistair Francis
,
18:10
[PATCH v2 1/3] riscv/sifive_u: Fix up file ordering
,
Alistair Francis
,
18:09
Re: [PATCH v2] riscv: sifive_u: Add a "serial" property for board serial number
,
Palmer Dabbelt
,
18:00
Re: [PATCH v1 1/1] target/riscv: Don't set write permissions on dirty PTEs
,
Richard Henderson
,
12:34
Re: [PATCH v1 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC
,
Bin Meng
,
09:47
Re: [PATCH v1 1/3] riscv/sifive_u: Fix up file ordering
,
Bin Meng
,
09:10
Re: [PATCH v4 2/3] linux-user/syscall: Add support for clock_gettime64/clock_settime64
,
Laurent Vivier
,
04:58
Re: [PATCH v4 2/3] linux-user/syscall: Add support for clock_gettime64/clock_settime64
,
Aleksandar Markovic
,
02:59
March 03, 2020
[PATCH v1 3/3] riscv/sifive_u: Add a serial property to the sifive_u machine
,
Alistair Francis
,
20:36
[PATCH v1 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC
,
Alistair Francis
,
20:36
[PATCH v1 1/3] riscv/sifive_u: Fix up file ordering
,
Alistair Francis
,
20:36
[PATCH v1 0/3] hw/riscv: Add a serial property to the sifive_u machine
,
Alistair Francis
,
20:36
[PATCH v1 1/1] target/riscv: Don't set write permissions on dirty PTEs
,
Alistair Francis
,
20:24
[PATCH v4 3/3] linux-user/riscv: Update the syscall_nr's to the 5.5 kernel
,
Alistair Francis
,
19:52
[PATCH v4 1/3] linux-user: Protect more syscalls
,
Alistair Francis
,
19:52
[PATCH v4 2/3] linux-user/syscall: Add support for clock_gettime64/clock_settime64
,
Alistair Francis
,
19:52
[PATCH v4 0/3] linux-user: generate syscall_nr.sh for RISC-V
,
Alistair Francis
,
19:52
Re: [PATCH] cpu: Use DeviceClass reset instead of a special CPUClass reset
,
Philippe Mathieu-Daudé
,
19:10
Re: [PATCH] cpu: Use DeviceClass reset instead of a special CPUClass reset
,
David Gibson
,
17:22
Re: [PATCH] cpu: Use DeviceClass reset instead of a special CPUClass reset
,
Eduardo Habkost
,
13:46
Re: [PATCH] cpu: Use DeviceClass reset instead of a special CPUClass reset
,
Richard Henderson
,
13:42
Re: [PATCH] cpu: Use DeviceClass reset instead of a special CPUClass reset
,
Peter Maydell
,
13:36
Re: [PATCH] cpu: Use DeviceClass reset instead of a special CPUClass reset
,
Philippe Mathieu-Daudé
,
13:33
Re: [PATCH] cpu: Use DeviceClass reset instead of a special CPUClass reset
,
Philippe Mathieu-Daudé
,
09:19
[PATCH v2 3/3] hw/riscv/spike: Allow more than one CPUs
,
Anup Patel
,
09:01
[PATCH v2 1/3] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
,
Anup Patel
,
09:01
[PATCH v2 2/3] hw/riscv/spike: Allow loading firmware separately using -bios option
,
Anup Patel
,
09:01
[PATCH v2 0/3] RISC-V Spike machine improvements
,
Anup Patel
,
09:01
Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 3
,
Peter Maydell
,
07:04
Re: [PATCH] cpu: Use DeviceClass reset instead of a special CPUClass reset
,
no-reply
,
05:13
Re: [PATCH] cpu: Use DeviceClass reset instead of a special CPUClass reset
,
no-reply
,
05:12
Re: [PATCH] cpu: Use DeviceClass reset instead of a special CPUClass reset
,
no-reply
,
05:12
Re: [PATCH] cpu: Use DeviceClass reset instead of a special CPUClass reset
,
no-reply
,
05:10
[PATCH] cpu: Use DeviceClass reset instead of a special CPUClass reset
,
Peter Maydell
,
05:05
Re: [PATCH v2] riscv: sifive_u: Add a "serial" property for board serial number
,
Bin Meng
,
04:30
March 02, 2020
[PULL 32/38] target/riscv: Set htval and mtval2 on execptions
,
Palmer Dabbelt
,
19:51
[PULL 37/38] target/riscv: Emulate TIME CSRs for privileged mode
,
Palmer Dabbelt
,
19:51
[PULL 36/38] riscv: virt: Allow PCI address 0
,
Palmer Dabbelt
,
19:51
[PULL 38/38] hw/riscv: Provide rdtime callback for TCG in CLINT emulation
,
Palmer Dabbelt
,
19:51
[PULL 35/38] target/riscv: Allow enabling the Hypervisor extension
,
Palmer Dabbelt
,
19:51
[PULL 34/38] target/riscv: Add the MSTATUS_MPV_ISSET helper macro
,
Palmer Dabbelt
,
19:51
[PULL 28/38] target/riscv: Respect MPRV and SPRV for floating point ops
,
Palmer Dabbelt
,
19:51
[PULL 27/38] target/riscv: Mark both sstatus and msstatus_hs as dirty
,
Palmer Dabbelt
,
19:51
[PULL 26/38] target/riscv: Disable guest FP support based on virtual status
,
Palmer Dabbelt
,
19:51
[PULL 25/38] target/riscv: Only set TB flags with FP status if enabled
,
Palmer Dabbelt
,
19:51
[PULL 29/38] target/riscv: Allow specifying MMU stage
,
Palmer Dabbelt
,
19:51
[PULL 33/38] target/riscv: Add support for the 32-bit MSTATUSH CSR
,
Palmer Dabbelt
,
19:51
[PULL 24/38] target/riscv: Remove the hret instruction
,
Palmer Dabbelt
,
19:51
[PULL 20/38] target/riscv: Generate illegal instruction on WFI when V=1
,
Palmer Dabbelt
,
19:51
[PULL 23/38] target/riscv: Add hfence instructions
,
Palmer Dabbelt
,
19:51
[PULL 19/38] target/ricsv: Flush the TLB on virtulisation mode changes
,
Palmer Dabbelt
,
19:51
[PULL 30/38] target/riscv: Implement second stage MMU
,
Palmer Dabbelt
,
19:50
[PULL 31/38] target/riscv: Raise the new execptions when 2nd stage translation fails
,
Palmer Dabbelt
,
19:50
[PULL 22/38] target/riscv: Add Hypervisor trap return support
,
Palmer Dabbelt
,
19:50
[PULL 13/38] target/riscv: Add Hypervisor machine CSRs accesses
,
Palmer Dabbelt
,
19:50
[PULL 18/38] target/riscv: Add support for virtual interrupt setting
,
Palmer Dabbelt
,
19:50
[PULL 12/38] target/riscv: Add Hypervisor virtual CSRs accesses
,
Palmer Dabbelt
,
19:50
[PULL 10/38] target/riscv: Dump Hypervisor registers if enabled
,
Palmer Dabbelt
,
19:50
[PULL 16/38] target/riscv: Extend the MIE CSR to support virtulisation
,
Palmer Dabbelt
,
19:50
[PULL 15/38] target/riscv: Set VS bits in mideleg for Hyp extension
,
Palmer Dabbelt
,
19:50
[PULL 04/38] target/riscv: Add support for the new execption numbers
,
Palmer Dabbelt
,
19:50
[PULL 21/38] target/riscv: Add hypvervisor trap support
,
Palmer Dabbelt
,
19:50
[PULL 17/38] target/riscv: Extend the SIP CSR to support virtulisation
,
Palmer Dabbelt
,
19:50
[PULL 14/38] target/riscv: Add virtual register swapping function
,
Palmer Dabbelt
,
19:50
[PULL 07/38] target/riscv: Add the force HS exception mode
,
Palmer Dabbelt
,
19:49
[PULL 06/38] target/riscv: Add the virtulisation mode
,
Palmer Dabbelt
,
19:49
[PULL 09/38] target/riscv: Print priv and virt in disas log
,
Palmer Dabbelt
,
19:49
[PULL 11/38] target/riscv: Add Hypervisor CSR access functions
,
Palmer Dabbelt
,
19:49
[PULL 08/38] target/riscv: Fix CSR perm checking for HS mode
,
Palmer Dabbelt
,
19:49
[PULL 03/38] target/riscv: Add the Hypervisor CSRs to CPUState
,
Palmer Dabbelt
,
19:49
[PULL 05/38] target/riscv: Rename the H irqs to VS irqs
,
Palmer Dabbelt
,
19:49
[PULL 01/38] target/riscv: Convert MIP CSR to target_ulong
,
Palmer Dabbelt
,
19:49
[PULL 02/38] target/riscv: Add the Hypervisor extension
,
Palmer Dabbelt
,
19:49
[PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 3
,
Palmer Dabbelt
,
19:49
Re: [PATCH v2] riscv: sifive_u: Add a "serial" property for board serial number
,
Alistair Francis
,
19:07
March 01, 2020
Re: [PATCH v3 1/2] target/riscv: Emulate TIME CSRs for privileged mode
,
Bin Meng
,
03:23
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