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Re: [RFC 08/15] target/riscv: rvb: single-bit instructions
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From: |
Richard Henderson |
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Subject: |
Re: [RFC 08/15] target/riscv: rvb: single-bit instructions |
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Date: |
Thu, 19 Nov 2020 12:05:24 -0800 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
> +static void gen_sbop_shamt(TCGv ret, TCGv shamt)
> +{
> + tcg_gen_andi_tl(ret, shamt, TARGET_LONG_BITS - 1);
> +}
> +
> +static void gen_sbop_common(TCGv ret, TCGv shamt)
> +{
> + TCGv t;
> + t = tcg_temp_new();
All of the places where you declare then initialize on the next line, please
merge them:
TCGv t = tcg_temp_new();
It would be nice to share more code between the normal and *w versions. As it
is, there's a *lot* of repetition with only TARGET_LONG_BITS vs 32 separating
them.
> + tcg_gen_not_tl(mask, mask);
> + tcg_gen_and_tl(ret, arg1, mask);
andc.
r~
- Re: [RFC 03/15] target/riscv: rvb: count bits set, (continued)
- [RFC 04/15] target/riscv: rvb: logic-with-negate, frank . chang, 2020/11/18
- [RFC 05/15] target/riscv: rvb: pack two words into one register, frank . chang, 2020/11/18
- [RFC 06/15] target/riscv: rvb: min/max instructions, frank . chang, 2020/11/18
- [RFC 07/15] target/riscv: rvb: sign-extend instructions, frank . chang, 2020/11/18
- [RFC 08/15] target/riscv: rvb: single-bit instructions, frank . chang, 2020/11/18
- [RFC 09/15] target/riscv: rvb: shift ones, frank . chang, 2020/11/18
- [RFC 10/15] target/riscv: rvb: rotate (left/right), frank . chang, 2020/11/18
- [RFC 11/15] target/riscv: rvb: generalized reverse, frank . chang, 2020/11/18
- [RFC 12/15] target/riscv: rvb: generalized or-combine, frank . chang, 2020/11/18