[PATCH] target/riscv: replace TARGET_LONG_BITS in gdbstub

[Frédéric Pétrot]

Now that we have misa xlen, use that in riscv gdbstub.c instead of the
TARGET_LONG_BITS define, and use riscv_cpu_mxl_bits to provide the number of
bits in a consistent way.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
---
 target/riscv/gdbstub.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 9ed049c29e..1602f76d2b 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -305,7 +305,7 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int 
base_reg)
     CPURISCVState *env = &cpu->env;
     GString *s = g_string_new(NULL);
     riscv_csr_predicate_fn predicate;
-    int bitsize = 16 << env->misa_mxl_max;
+    int bitsize = riscv_cpu_mxl_bits(env);
     int i;
 
     /* Until gdb knows about 128-bit registers */
@@ -385,10 +385,11 @@ static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int 
base_reg)
 
     for (i = 0; i < 7; i++) {
         g_string_append_printf(s,
-                               "<reg name=\"%s\" bitsize=\"%d\""
+                               "<reg name=\"%s\" bitsize=\"%lu\""
                                " regnum=\"%d\" group=\"vector\""
                                " type=\"int\"/>",
-                               vector_csrs[i], TARGET_LONG_BITS, base_reg++);
+                               vector_csrs[i], riscv_cpu_mxl_bits(&cpu->env),
+                               base_reg++);
         num_regs++;
     }
 
-- 
2.35.1