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Re: [PATCH v11 3/5] target/riscv: generate virtual instruction exception
From: |
Alistair Francis |
Subject: |
Re: [PATCH v11 3/5] target/riscv: generate virtual instruction exception |
Date: |
Thu, 10 Nov 2022 09:17:04 +1000 |
On Sun, Oct 16, 2022 at 10:58 PM Mayuresh Chitale
<mchitale@ventanamicro.com> wrote:
>
> This patch adds a mechanism to generate a virtual instruction
> instruction exception instead of an illegal instruction exception
> during instruction decode when virt is enabled.
>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/translate.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index db123da5ec..8b0bd38bb2 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -76,6 +76,7 @@ typedef struct DisasContext {
> to reset this known value. */
> int frm;
> RISCVMXL ol;
> + bool virt_inst_excp;
> bool virt_enabled;
> const RISCVCPUConfig *cfg_ptr;
> bool hlsx;
> @@ -243,7 +244,11 @@ static void gen_exception_illegal(DisasContext *ctx)
> {
> tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
> offsetof(CPURISCVState, bins));
> - generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
> + if (ctx->virt_inst_excp) {
> + generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
> + } else {
> + generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
> + }
> }
>
> static void gen_exception_inst_addr_mis(DisasContext *ctx)
> @@ -1062,6 +1067,7 @@ static void decode_opc(CPURISCVState *env, DisasContext
> *ctx, uint16_t opcode)
> { has_XVentanaCondOps_p, decode_XVentanaCodeOps },
> };
>
> + ctx->virt_inst_excp = false;
> /* Check for compressed insn */
> if (insn_len(opcode) == 2) {
> if (!has_ext(ctx, RVC)) {
> --
> 2.25.1
>
>
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