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Re: [PATCH v1 4/4] target/riscv: Add itrigger_enabled field to CPURISCVS
From: |
Alistair Francis |
Subject: |
Re: [PATCH v1 4/4] target/riscv: Add itrigger_enabled field to CPURISCVState |
Date: |
Fri, 11 Nov 2022 10:54:45 +1000 |
On Thu, Nov 10, 2022 at 3:35 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 11/10/22 13:15, LIU Zhiwei wrote:
> >>> +static int debug_post_load(void *opaque, int version_id)
> >>> +{
> >>> + RISCVCPU *cpu = opaque;
> >>> + CPURISCVState *env = &cpu->env;
> >>> +
> >>> + if (icount_enabled()) {
> >>> + env->itrigger_enabled = riscv_itrigger_enabled(env);
> >>> + }
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> static const VMStateDescription vmstate_debug = {
> >>> .name = "cpu/debug",
> >>> .version_id = 2,
> >>> .minimum_version_id = 2,
> >> The versions here should be bumped
> >
> > Hi Alistair and Richard,
> >
> > I am not sure if we should bump versions when just add post_load callback
> > without adding
> > new fields. I once upstreamed a patch
> > with a similar change but not bumping version.
>
> Simply adding a post_load does not require a version bump.
Ah, my mistake then
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
>
> r~