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[PATCH v2 2/8] target/riscv: add support for Zca and Zcf extensions
From: |
Weiwei Li |
Subject: |
[PATCH v2 2/8] target/riscv: add support for Zca and Zcf extensions |
Date: |
Sun, 13 Nov 2022 10:32:45 +0800 |
Add check for Zca and Zcf extensions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
target/riscv/translate.c | 16 ++++++++++++++--
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
index 5c69b88d1e..0d73b919ce 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -56,7 +56,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
gen_set_pc(ctx, cpu_pc);
- if (!has_ext(ctx, RVC)) {
+ if (!ctx->cfg_ptr->ext_zca) {
TCGv t0 = tcg_temp_new();
misaligned = gen_new_label();
@@ -178,7 +178,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond
cond)
gen_set_label(l); /* branch taken */
- if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
+ if (!ctx->cfg_ptr->ext_zca && ((ctx->base.pc_next + a->imm) & 0x3)) {
/* misaligned */
gen_exception_inst_addr_mis(ctx);
} else {
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 2ab8772ebe..0514e43fd3 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -557,7 +557,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong
imm)
/* check misaligned: */
next_pc = ctx->base.pc_next + imm;
- if (!has_ext(ctx, RVC)) {
+ if (!ctx->cfg_ptr->ext_zca) {
if ((next_pc & 0x3) != 0) {
gen_exception_inst_addr_mis(ctx);
return;
@@ -1097,7 +1097,19 @@ static void decode_opc(CPURISCVState *env, DisasContext
*ctx, uint16_t opcode)
ctx->virt_inst_excp = false;
/* Check for compressed insn */
if (insn_len(opcode) == 2) {
- if (!has_ext(ctx, RVC)) {
+ /*
+ * Zca support all of the existing C extension, excluding all
+ * compressed floating point loads and stores
+ * Zcf(RV32 only) support c.flw, c.flwsp, c.fsw, c.fswsp
+ */
+ if (!ctx->cfg_ptr->ext_zca) {
+ gen_exception_illegal(ctx);
+ } else if ((get_xl_max(ctx) == MXL_RV32) &&
+ !ctx->cfg_ptr->ext_zcf &&
+ (((opcode & 0xe003) == 0x6000) ||
+ ((opcode & 0xe003) == 0x6002) ||
+ ((opcode & 0xe003) == 0xe000) ||
+ ((opcode & 0xe003) == 0xe002))) {
gen_exception_illegal(ctx);
} else {
ctx->opcode = opcode;
--
2.25.1
- [PATCH v2 0/8] support subsets of code size reduction extension, Weiwei Li, 2022/11/12
- [PATCH v2 3/8] target/riscv: add support for Zcd extension, Weiwei Li, 2022/11/12
- [PATCH v2 1/8] target/riscv: add cfg properties for Zc* extension, Weiwei Li, 2022/11/12
- [PATCH v2 4/8] target/riscv: add support for Zcb extension, Weiwei Li, 2022/11/12
- [PATCH v2 2/8] target/riscv: add support for Zca and Zcf extensions,
Weiwei Li <=
- [PATCH v2 5/8] target/riscv: add support for Zcmp extension, Weiwei Li, 2022/11/12
- [PATCH v2 7/8] target/riscv: expose properties for Zc* extension, Weiwei Li, 2022/11/12
- [PATCH v2 8/8] disas/riscv.c: add disasm support for Zc*, Weiwei Li, 2022/11/12
- [PATCH v2 6/8] target/riscv: add support for Zcmt extension, Weiwei Li, 2022/11/12