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Re: [PATCH v2 3/3] hw/{misc, riscv}: pfsoc: add system controller as uni
From: |
Conor Dooley |
Subject: |
Re: [PATCH v2 3/3] hw/{misc, riscv}: pfsoc: add system controller as unimplemented |
Date: |
Sun, 13 Nov 2022 21:19:59 +0000 |
On Sun, Nov 13, 2022 at 08:30:42PM +0100, Philippe Mathieu-Daudé wrote:
> Hi Conor,
>
> On 12/11/22 14:34, Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > The system controller on PolarFire SoC is access via a mailbox. The
> > control registers for this mailbox lie in the "IOSCB" region & the
> > interrupt is cleared via write to the "SYSREG" region. It also has a
> > QSPI controller, usually connected to a flash chip, that is used for
> > storing FPGA bitstreams and used for In-Application Programming (IAP).
> >
> > Linux has an implementation of the system controller, through which the
> > hwrng is accessed, leading to load/store access faults.
> >
> > Add the QSPI as unimplemented and a very basic (effectively
> > unimplemented) version of the system controller's mailbox. Rather than
> > purely marking the regions as unimplemented, service the mailbox
> > requests by reporting failures and raising the interrupt so a guest can
> > better handle the lack of support.
> >
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> > hw/misc/mchp_pfsoc_ioscb.c | 59 ++++++++++++++++++++++++++++-
> > hw/misc/mchp_pfsoc_sysreg.c | 19 ++++++++--
> > hw/riscv/microchip_pfsoc.c | 6 +++
> > include/hw/misc/mchp_pfsoc_ioscb.h | 3 ++
> > include/hw/misc/mchp_pfsoc_sysreg.h | 1 +
> > include/hw/riscv/microchip_pfsoc.h | 1 +
> > 6 files changed, 83 insertions(+), 6 deletions(-)
>
> > @@ -52,10 +54,18 @@ static uint64_t mchp_pfsoc_sysreg_read(void *opaque,
> > hwaddr offset,
> > static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset,
> > uint64_t value, unsigned size)
> > {
> > - qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
> > - "(size %d, value 0x%" PRIx64
> > - ", offset 0x%" HWADDR_PRIx ")\n",
> > - __func__, size, value, offset);
> > + MchpPfSoCSysregState *s = opaque;
> > + qemu_irq_lower(s->irq);
>
> Is this always lowered IRQ line wanted? ...
>
> > + switch (offset) {
> > + case MESSAGE_INT:
> > + qemu_irq_lower(s->irq);
>
> ... since we do it here.
Probably just me pressing the y key instead of the d one.
I'll sort that out for v3, thanks!
> > + break;
> > + default:
> > + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
> > + "(size %d, value 0x%" PRIx64
> > + ", offset 0x%" HWADDR_PRIx ")\n",
> > + __func__, size, value, offset);
> > + }
> > }
>
>