Re: [PATCH v5 1/9] target/riscv: add cfg properties for Zc* extension

[Alistair Francis]

On Fri, Nov 18, 2022 at 10:45 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension
> Add check for these properties
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> Cc: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 43 +++++++++++++++++++++++++++++++++++++++++++
>  target/riscv/cpu.h |  6 ++++++
>  2 files changed, 49 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 042fd541b4..1ab04ab246 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -805,6 +805,49 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>              }
>          }
>
> +        if (cpu->cfg.ext_c) {
> +            cpu->cfg.ext_zca = true;
> +            if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) {
> +                cpu->cfg.ext_zcf = true;
> +            }
> +            if (cpu->cfg.ext_d) {
> +                cpu->cfg.ext_zcd = true;
> +            }
> +        }
> +
> +        if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
> +            error_setg(errp, "Zcf extension is only relevant to RV32");
> +            return;
> +        }
> +
> +        if (!cpu->cfg.ext_f && cpu->cfg.ext_zcf) {
> +            error_setg(errp, "Zcf extension requires F extension");
> +            return;
> +        }
> +
> +        if (!cpu->cfg.ext_d && cpu->cfg.ext_zcd) {
> +            error_setg(errp, "Zcd extensionrequires D extension");
> +            return;
> +        }
> +
> +        if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb ||
> +             cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) {
> +            error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca "
> +                             "extension");
> +            return;
> +        }
> +
> +        if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) {
> +            error_setg(errp, "Zcmp/Zcmt extensions are incompatible with "
> +                             "Zcd extension");
> +            return;
> +        }
> +
> +        if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) {
> +            error_setg(errp, "Zcmt extension requires Zicsr extension");
> +            return;
> +        }
> +
>          if (cpu->cfg.ext_zk) {
>              cpu->cfg.ext_zkn = true;
>              cpu->cfg.ext_zkr = true;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 9bd539d77a..6e915b6937 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -434,6 +434,12 @@ struct RISCVCPUConfig {
>      bool ext_zbkc;
>      bool ext_zbkx;
>      bool ext_zbs;
> +    bool ext_zca;
> +    bool ext_zcb;
> +    bool ext_zcd;
> +    bool ext_zcf;
> +    bool ext_zcmp;
> +    bool ext_zcmt;
>      bool ext_zk;
>      bool ext_zkn;
>      bool ext_zknd;
> --
> 2.25.1
>
>