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Re: [PATCH v5 4/9] target/riscv: add support for Zcd extension
From: |
Alistair Francis |
Subject: |
Re: [PATCH v5 4/9] target/riscv: add support for Zcd extension |
Date: |
Mon, 21 Nov 2022 17:20:40 +1000 |
On Fri, Nov 18, 2022 at 10:40 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Separate c_fld/c_fsd from fld/fsd to add additional check for
> c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse
> their encodings
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn16.decode | 8 ++++----
> target/riscv/insn_trans/trans_rvd.c.inc | 18 ++++++++++++++++++
> 2 files changed, 22 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
> index f3ea650325..b62664b6af 100644
> --- a/target/riscv/insn16.decode
> +++ b/target/riscv/insn16.decode
> @@ -97,12 +97,12 @@
> }
> {
> lq 001 ... ... .. ... 00 @cl_q
> - fld 001 ... ... .. ... 00 @cl_d
> + c_fld 001 ... ... .. ... 00 @cl_d
> }
> lw 010 ... ... .. ... 00 @cl_w
> {
> sq 101 ... ... .. ... 00 @cs_q
> - fsd 101 ... ... .. ... 00 @cs_d
> + c_fsd 101 ... ... .. ... 00 @cs_d
> }
> sw 110 ... ... .. ... 00 @cs_w
>
> @@ -148,7 +148,7 @@ addw 100 1 11 ... 01 ... 01 @cs_2
> slli 000 . ..... ..... 10 @c_shift2
> {
> lq 001 ... ... .. ... 10 @c_lqsp
> - fld 001 . ..... ..... 10 @c_ldsp
> + c_fld 001 . ..... ..... 10 @c_ldsp
> }
> {
> illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=0
> @@ -166,7 +166,7 @@ slli 000 . ..... ..... 10 @c_shift2
> }
> {
> sq 101 ... ... .. ... 10 @c_sqsp
> - fsd 101 ...... ..... 10 @c_sdsp
> + c_fsd 101 ...... ..... 10 @c_sdsp
> }
> sw 110 . ..... ..... 10 @c_swsp
>
> diff --git a/target/riscv/insn_trans/trans_rvd.c.inc
> b/target/riscv/insn_trans/trans_rvd.c.inc
> index 1397c1ce1c..def0d7abfe 100644
> --- a/target/riscv/insn_trans/trans_rvd.c.inc
> +++ b/target/riscv/insn_trans/trans_rvd.c.inc
> @@ -31,6 +31,12 @@
> } \
> } while (0)
>
> +#define REQUIRE_ZCD(ctx) do { \
> + if (!ctx->cfg_ptr->ext_zcd) { \
> + return false; \
> + } \
> +} while (0)
> +
> static bool trans_fld(DisasContext *ctx, arg_fld *a)
> {
> TCGv addr;
> @@ -57,6 +63,18 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
> return true;
> }
>
> +static bool trans_c_fld(DisasContext *ctx, arg_fld *a)
> +{
> + REQUIRE_ZCD(ctx);
> + return trans_fld(ctx, a);
> +}
> +
> +static bool trans_c_fsd(DisasContext *ctx, arg_fsd *a)
> +{
> + REQUIRE_ZCD(ctx);
> + return trans_fsd(ctx, a);
> +}
> +
> static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a)
> {
> REQUIRE_FPU;
> --
> 2.25.1
>
>
- [PATCH v5 0/9] support subsets of code size reduction extension, Weiwei Li, 2022/11/18
- [PATCH v5 4/9] target/riscv: add support for Zcd extension, Weiwei Li, 2022/11/18
- Re: [PATCH v5 4/9] target/riscv: add support for Zcd extension,
Alistair Francis <=
- [PATCH v5 5/9] target/riscv: add support for Zcb extension, Weiwei Li, 2022/11/18
- [PATCH v5 9/9] disas/riscv.c: add disasm support for Zc*, Weiwei Li, 2022/11/18
- [PATCH v5 2/9] target/riscv: add support for Zca extension, Weiwei Li, 2022/11/18
- [PATCH v5 6/9] target/riscv: add support for Zcmp extension, Weiwei Li, 2022/11/18
- [PATCH v5 8/9] target/riscv: expose properties for Zc* extension, Weiwei Li, 2022/11/18
- [PATCH v5 1/9] target/riscv: add cfg properties for Zc* extension, Weiwei Li, 2022/11/18