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Re: [PATCH] target/riscv: support cache-related PMU events in virtual mo
From: |
Alistair Francis |
Subject: |
Re: [PATCH] target/riscv: support cache-related PMU events in virtual mode |
Date: |
Fri, 25 Nov 2022 15:10:39 +1000 |
On Wed, Nov 23, 2022 at 7:07 PM Jim Shu <jim.shu@sifive.com> wrote:
>
> let tlb_fill() function also increments PMU counter when it is from
> two-stage translation, so QEMU could also monitor these PMU events when
> CPU runs in VS/VU mode (like running guest OS).
>
> Signed-off-by: Jim Shu <jim.shu@sifive.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 278d163803..a52a9b14d7 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -1248,6 +1248,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address,
> int size,
> }
> }
>
> + pmu_tlb_fill_incr_ctr(cpu, access_type);
> if (riscv_cpu_virt_enabled(env) ||
> ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&
> access_type != MMU_INST_FETCH)) {
> @@ -1311,7 +1312,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address,
> int size,
> }
> }
> } else {
> - pmu_tlb_fill_incr_ctr(cpu, access_type);
> /* Single stage lookup */
> ret = get_physical_address(env, &pa, &prot, address, NULL,
> access_type, mmu_idx, true, false, false);
> --
> 2.17.1
>
>