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[RFC PATCH 24/39] target/riscv: add zvknh cpu properties
From: |
Lawrence Hunter |
Subject: |
[RFC PATCH 24/39] target/riscv: add zvknh cpu properties |
Date: |
Thu, 19 Jan 2023 14:35:13 +0000 |
From: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 660af57038..50bc96be5c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -101,6 +101,8 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f),
ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f),
ISA_EXT_DATA_ENTRY(zvkb, true, PRIV_VERSION_1_12_0, ext_zvkb),
+ ISA_EXT_DATA_ENTRY(zvknha, true, PRIV_VERSION_1_12_0, ext_zvknha),
+ ISA_EXT_DATA_ENTRY(zvknhb, true, PRIV_VERSION_1_12_0, ext_zvknhb),
ISA_EXT_DATA_ENTRY(zvkns, true, PRIV_VERSION_1_12_0, ext_zvkns),
ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 56008ef9b9..ebee902806 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -462,6 +462,8 @@ struct RISCVCPUConfig {
bool ext_zve32f;
bool ext_zve64f;
bool ext_zvkb;
+ bool ext_zvknha;
+ bool ext_zvknhb;
bool ext_zvkns;
bool ext_zmmul;
bool ext_smaia;
--
2.39.1
- [RFC PATCH 06/39] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] decoding, translation and execution support, (continued)
- [RFC PATCH 06/39] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] decoding, translation and execution support, Lawrence Hunter, 2023/01/19
- [RFC PATCH 05/39] target/riscv: Add vclmulh.vx decoding, translation and execution support, Lawrence Hunter, 2023/01/19
- [RFC PATCH 17/39] target/riscv: Add vaesdm.vs decoding, translation and execution support, Lawrence Hunter, 2023/01/19
- [RFC PATCH 11/39] target/riscv: add zvkns cpu property, Lawrence Hunter, 2023/01/19
- [RFC PATCH 28/39] target/riscv: add zvksh cpu property, Lawrence Hunter, 2023/01/19
- [RFC PATCH 25/39] target/riscv: Add vsha2ms.vv decoding, translation and execution support, Lawrence Hunter, 2023/01/19
- [RFC PATCH 27/39] target/riscv: expose zvknh cpu properties, Lawrence Hunter, 2023/01/19
- [RFC PATCH 10/39] target/riscv: expose zvkb cpu property, Lawrence Hunter, 2023/01/19
- [RFC PATCH 18/39] target/riscv: Add vaesz.vs decoding, translation and execution support, Lawrence Hunter, 2023/01/19
- [RFC PATCH 12/39] target/riscv: Add vaesef.vv decoding, translation and execution support, Lawrence Hunter, 2023/01/19
- [RFC PATCH 24/39] target/riscv: add zvknh cpu properties,
Lawrence Hunter <=
- [RFC PATCH 03/39] target/riscv: Add vclmul.vx decoding, translation and execution support, Lawrence Hunter, 2023/01/19
- [RFC PATCH 13/39] target/riscv: Add vaesef.vs decoding, translation and execution support, Lawrence Hunter, 2023/01/19
- [RFC PATCH 21/39] target/riscv: Add vaeskf1.vi decoding, translation and execution support, Lawrence Hunter, 2023/01/19
- [RFC PATCH 19/39] target/riscv: Add vaesem.vv decoding, translation and execution support, Lawrence Hunter, 2023/01/19
- [RFC PATCH 08/39] target/riscv: Add vrev8.v decoding, translation and execution support, Lawrence Hunter, 2023/01/19
- [RFC PATCH 23/39] target/riscv: expose zvkns cpu property, Lawrence Hunter, 2023/01/19
- [RFC PATCH 29/39] target/riscv: Add vsm3me.vv decoding, translation and execution support, Lawrence Hunter, 2023/01/19
- [RFC PATCH 22/39] target/riscv: Add vaeskf2.vi decoding, translation and execution support, Lawrence Hunter, 2023/01/19
- [RFC PATCH 26/39] target/riscv: Add vsha2c[hl].vv decoding, translation and execution support, Lawrence Hunter, 2023/01/19
- [RFC PATCH 36/39] crypto: Add SM4 constant parameter CK., Lawrence Hunter, 2023/01/19