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[RFC PATCH 33/39] target/riscv: Add vghmac.vv decoding, translation and
From: |
Lawrence Hunter |
Subject: |
[RFC PATCH 33/39] target/riscv: Add vghmac.vv decoding, translation and execution support |
Date: |
Thu, 19 Jan 2023 14:35:22 +0000 |
Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
---
target/riscv/helper.h | 2 +
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvzvkg.c.inc | 8 ++++
target/riscv/translate.c | 1 +
target/riscv/vcrypto_helper.c | 45 ++++++++++++++++++++++
5 files changed, 59 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_rvzvkg.c.inc
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index a82103ead9..6272294d50 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1199,3 +1199,5 @@ DEF_HELPER_5(vsha2cl_vv, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32)
+
+DEF_HELPER_5(vghmac_vv, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 4a50114e92..ff044f8288 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -930,3 +930,6 @@ vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111
@r_vm_1
# *** RV64 Zvksh vector crypto extensions ***
vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1
vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1
+
+# *** RV64 Zvkg vector crypto extension ***
+vghmac_vv 101100 1 ..... ..... 010 ..... 1110111 @r_vm_1
diff --git a/target/riscv/insn_trans/trans_rvzvkg.c.inc
b/target/riscv/insn_trans/trans_rvzvkg.c.inc
new file mode 100644
index 0000000000..576f5d39c4
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvzvkg.c.inc
@@ -0,0 +1,8 @@
+static bool vghmac_check(DisasContext *s, arg_rmrr *a)
+{
+ return opivv_check(s, a) &&
+ s->vstart % 4 == 0 &&
+ s->sew == MO_32;
+}
+
+GEN_VV_UNMASKED_TRANS(vghmac_vv, vghmac_check)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9ca2cec23a..0bc1c9db65 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1067,6 +1067,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase,
target_ulong pc)
#include "insn_trans/trans_rvzvkns.c.inc"
#include "insn_trans/trans_rvzvknh.c.inc"
#include "insn_trans/trans_rvzvksh.c.inc"
+#include "insn_trans/trans_rvzvkg.c.inc"
#include "insn_trans/trans_privileged.c.inc"
#include "insn_trans/trans_svinval.c.inc"
#include "insn_trans/trans_xventanacondops.c.inc"
diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
index 478e652c9b..a309ac3f03 100644
--- a/target/riscv/vcrypto_helper.c
+++ b/target/riscv/vcrypto_helper.c
@@ -827,3 +827,48 @@ void HELPER(vsm3c_vi)(void *vd_vptr, void *vs2_vptr,
uint32_t uimm,
vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz);
env->vstart = 0;
}
+
+void HELPER(vghmac_vv)(void *vd_vptr, void *vs1_vptr, void *vs2_vptr,
+ CPURISCVState *env, uint32_t desc)
+{
+ uint64_t *vd = vd_vptr;
+ uint64_t *vs1 = vs1_vptr;
+ uint64_t *vs2 = vs2_vptr;
+ uint32_t vta = vext_vta(desc);
+ uint32_t total_elems = vext_get_total_elems(env, desc, 4);
+
+ if (env->vl % 4 != 0) {
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ }
+
+ for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) {
+ __uint128_t Y = reverse_bits_byte_8(vd[i * 2 + 0]) |
+ ((__uint128_t)reverse_bits_byte_8(vd[i * 2 + 1]) <<
64);
+ __uint128_t H = reverse_bits_byte_8(vs1[i * 2 + 0]) |
+ ((__uint128_t)reverse_bits_byte_8(vs1[i * 2 + 1]) <<
64);
+ __uint128_t X = vs2[i * 2 + 0] | ((__uint128_t)vs2[i * 2 + 1] << 64);
+ __uint128_t Z = 0;
+
+ for (uint j = 0; j < 128; j++) {
+ if ((Y >> j) & 1) {
+ Z ^= H;
+ }
+ bool reduce = ((H >> 127) & 1);
+ H = H << 1;
+ if (reduce) {
+ H ^= 0x87;
+ }
+ }
+
+ Z = reverse_bits_byte_8(Z & UINT64_MAX) |
+ ((__uint128_t)reverse_bits_byte_8((Z >> 64) & UINT64_MAX) << 64);
+
+ Z = Z ^ X;
+
+ vd[i * 2 + 0] = Z & UINT64_MAX;
+ vd[i * 2 + 1] = (Z >> 64) & UINT64_MAX;
+ }
+ /* set tail elements to 1s */
+ vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4);
+ env->vstart = 0;
+}
--
2.39.1
- [RFC PATCH 22/39] target/riscv: Add vaeskf2.vi decoding, translation and execution support, (continued)
- [RFC PATCH 22/39] target/riscv: Add vaeskf2.vi decoding, translation and execution support, Lawrence Hunter, 2023/01/19
- [RFC PATCH 26/39] target/riscv: Add vsha2c[hl].vv decoding, translation and execution support, Lawrence Hunter, 2023/01/19
- [RFC PATCH 36/39] crypto: Add SM4 constant parameter CK., Lawrence Hunter, 2023/01/19
- [RFC PATCH 34/39] target/riscv: expose zvkg cpu property, Lawrence Hunter, 2023/01/19
- [RFC PATCH 30/39] target/riscv: Add vsm3c.vi decoding, translation and execution support, Lawrence Hunter, 2023/01/19
- [RFC PATCH 38/39] target/riscv: Add Zvksed support, Lawrence Hunter, 2023/01/19
- [RFC PATCH 37/39] target/riscv: Add zvksed cfg property, Lawrence Hunter, 2023/01/19
- [RFC PATCH 35/39] crypto: Move SM4_SBOXWORD from target/riscv, Lawrence Hunter, 2023/01/19
- [RFC PATCH 39/39] target/riscv: Expose Zvksed property, Lawrence Hunter, 2023/01/19
- [RFC PATCH 32/39] target/riscv: add zvkg cpu property, Lawrence Hunter, 2023/01/19
- [RFC PATCH 33/39] target/riscv: Add vghmac.vv decoding, translation and execution support,
Lawrence Hunter <=
- [RFC PATCH 31/39] target/riscv: expose zvksh cpu property, Lawrence Hunter, 2023/01/19
- Re: [RFC PATCH 00/39] Add RISC-V cryptography extensions standardisation, Frank Chang, 2023/01/19
- Fwd: [RFC PATCH 00/39] Add RISC-V cryptography extensions standardisation, Lawrence Hunter, 2023/01/26