Re: Fwd: [RFC PATCH 00/39] Add RISC-V cryptography extensions standardisation

[Alistair Francis]

On Thu, 2023-01-26 at 09:21 +0000, Lawrence Hunter wrote:
> Follow up for add RISC-V vector cryptography extensions
> standardisation
> RFC: we've not received any comments and would like to move this
> series
> towards getting merged. Does anyone have time to review it, and
> should
> we look at resubmitting for merging soon?

Hello,

This series never made it to the QEMU list. It looks like it was never
sent to the general qemu-devel mailing list.

When submitting patches can you please follow the steps here:
https://www.qemu.org/docs/master/devel/submitting-a-patch.html#submitting-your-patches

It's important that all patches are sent to the qemu-devel mailing list
(that's actually much more important then the RISC-V mailing list).

Alistair

> 
> ---------- Forwarded Message ---------
> 
> From: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
> Subject: [RFC PATCH 00/39] Add RISC-V cryptography extensions
> standardisation
> Date: Jan 19 2023, at 2:34 pm
> To: qemu-riscv@nongnu.org
> Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Lawrence
> Hunter <lawrence.hunter@codethink.co.uk>
> 
> 
> > This RFC introduces an implementation for the six instruction sets
> > of the draft RISC-V cryptography extensions standardisation
> > specification. Once the specification has been ratified we will
> > submit
> > these changes as a pull request email to this mailing list. Would
> > this
> > be prefered by instruction group or unified as in this RFC?
> > 
> > This patch set implements the instruction sets as per the 20221202
> > version of the specification (1).
> > 
> > Work performed by Dickon, Lawrence, Nazar, Kiran, and William from
> > Codethink
> > sponsored by SiFive, and Max Chou from SiFive.
> > 
> > 1. https://github.com/riscv/riscv-crypto/releases
> > 
> > Dickon Hood (1):
> >  target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] decoding,
> >    translation and execution support
> > 
> > Kiran Ostrolenk (4):
> >  target/riscv: Add vsha2ms.vv decoding, translation and execution
> >    support
> >  target/riscv: add zvksh cpu property
> >  target/riscv: Add vsm3c.vi decoding, translation and execution
> > support
> >  target/riscv: expose zvksh cpu property
> > 
> > Lawrence Hunter (16):
> >  target/riscv: Add vclmul.vv decoding, translation and execution
> >    support
> >  target/riscv: Add vclmul.vx decoding, translation and execution
> >    support
> >  target/riscv: Add vclmulh.vv decoding, translation and execution
> >    support
> >  target/riscv: Add vclmulh.vx decoding, translation and execution
> >    support
> >  target/riscv: Add vaesef.vv decoding, translation and execution
> >    support
> >  target/riscv: Add vaesef.vs decoding, translation and execution
> >    support
> >  target/riscv: Add vaesdf.vv decoding, translation and execution
> >    support
> >  target/riscv: Add vaesdf.vs decoding, translation and execution
> >    support
> >  target/riscv: Add vaesdm.vv decoding, translation and execution
> >    support
> >  target/riscv: Add vaesdm.vs decoding, translation and execution
> >    support
> >  target/riscv: Add vaesz.vs decoding, translation and execution
> > support
> >  target/riscv: Add vsha2c[hl].vv decoding, translation and
> > execution
> >    support
> >  target/riscv: Add vsm3me.vv decoding, translation and execution
> >    support
> >  target/riscv: add zvkg cpu property
> >  target/riscv: Add vghmac.vv decoding, translation and execution
> >    support
> >  target/riscv: expose zvkg cpu property
> > 
> > Max Chou (5):
> >  crypto: Move SM4_SBOXWORD from target/riscv
> >  crypto: Add SM4 constant parameter CK.
> >  target/riscv: Add zvksed cfg property
> >  target/riscv: Add Zvksed support
> >  target/riscv: Expose Zvksed property
> > 
> > Nazar Kazakov (10):
> >  target/riscv: add zvkb cpu property
> >  target/riscv: Add vrev8.v decoding, translation and execution
> > support
> >  target/riscv: Add vandn.[vv,vx,vi] decoding, translation and
> > execution
> >    support
> >  target/riscv: expose zvkb cpu property
> >  target/riscv: add zvkns cpu property
> >  target/riscv: Add vaeskf1.vi decoding, translation and execution
> >    support
> >  target/riscv: Add vaeskf2.vi decoding, translation and execution
> >    support
> >  target/riscv: expose zvkns cpu property
> >  target/riscv: add zvknh cpu properties
> >  target/riscv: expose zvknh cpu properties
> > 
> > William Salmon (3):
> >  target/riscv: Add vbrev8.v decoding, translation and execution
> > support
> >  target/riscv: Add vaesem.vv decoding, translation and execution
> >    support
> >  target/riscv: Add vaesem.vs decoding, translation and execution
> >    support
> > 
> > crypto/sm4.c                                 |   10 +
> > include/crypto/sm4.h                         |    8 +
> > include/qemu/bitops.h                        |   32 +
> > target/arm/crypto_helper.c                   |   10 +-
> > target/riscv/cpu.c                           |   15 +
> > target/riscv/cpu.h                           |    7 +
> > target/riscv/crypto_helper.c                 |    1 +
> > target/riscv/helper.h                        |   69 ++
> > target/riscv/insn32.decode                   |   48 +
> > target/riscv/insn_trans/trans_rvzvkb.c.inc   |  164 +++
> > target/riscv/insn_trans/trans_rvzvkg.c.inc   |    8 +
> > target/riscv/insn_trans/trans_rvzvknh.c.inc  |   47 +
> > target/riscv/insn_trans/trans_rvzvkns.c.inc  |  121 +++
> > target/riscv/insn_trans/trans_rvzvksed.c.inc |   38 +
> > target/riscv/insn_trans/trans_rvzvksh.c.inc  |   20 +
> > target/riscv/meson.build                     |    4 +-
> > target/riscv/translate.c                     |    6 +
> > target/riscv/vcrypto_helper.c                | 1013
> > ++++++++++++++++++
> > target/riscv/vector_helper.c                 |  242 +----
> > target/riscv/vector_internals.c              |   63 ++
> > target/riscv/vector_internals.h              |  226 ++++
> > 21 files changed, 1902 insertions(+), 250 deletions(-)
> > create mode 100644 target/riscv/insn_trans/trans_rvzvkb.c.inc
> > create mode 100644 target/riscv/insn_trans/trans_rvzvkg.c.inc
> > create mode 100644 target/riscv/insn_trans/trans_rvzvknh.c.inc
> > create mode 100644 target/riscv/insn_trans/trans_rvzvkns.c.inc
> > create mode 100644 target/riscv/insn_trans/trans_rvzvksed.c.inc
> > create mode 100644 target/riscv/insn_trans/trans_rvzvksh.c.inc
> > create mode 100644 target/riscv/vcrypto_helper.c
> > create mode 100644 target/riscv/vector_internals.c
> > create mode 100644 target/riscv/vector_internals.h
> > 
> > -- 
> > 2.39.1
> > 
> > 
> >