Re: [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension

qemu-riscv

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension

From:	Richard Henderson
Subject:	Re: [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension
Date:	Sun, 29 Jan 2023 19:43:43 -1000
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2

On 1/29/23 16:03, LIU Zhiwei wrote:

Thanks. It's a bug. We should load all memory addresses to  local TCG temps 
first.
Do you think we should probe all the memory addresses for the store pair instructions? Ifso, can we avoid the use of a helper function?

Depends on what the hardware does. Even with a trap in the middle the stores arerestartable, since no register state changes.

But if you'd like no changes verifying both stores, for this case you can pack the pairinto a larger data type: TCGv_i64 for pair of 32-bit, and TCGv_i128 for pair of 64-bit.Patches for TCGv_i128 [1] are just finishing review; patches to describe atomicity of thelarger operation are also on list [2]. Anyway, the idea is that you issue one TCG memoryoperation, the entire operation is validated, and then the stores happen.

The main reason is that assembler can do this check. Is it necessary to check 
this in QEMU?

Yes. Conciser what happens when the insn is encoded with .long. Does the hardware trapan illegal instruction? Is the behavior simply unspecified? The manual could be improvedto specify, akin to the Arm terms: UNDEFINED, CONSTRAINED UNPREDICTABLE, IMPLEMENTATIONDEFINED, etc.



r~

[1] 
https://patchew.org/QEMU/20230126043824.54819-1-richard.henderson@linaro.org/
[2] 
https://patchew.org/QEMU/20221118094754.242910-1-richard.henderson@linaro.org/

[Prev in Thread]

Current Thread

[Next in Thread]

Re: [PATCH v3 02/14] RISC-V: Adding XTheadSync ISA extension, (continued)
- [PATCH v3 03/14] RISC-V: Adding XTheadBa ISA extension, Christoph Muellner, 2023/01/24
- [PATCH v3 04/14] RISC-V: Adding XTheadBb ISA extension, Christoph Muellner, 2023/01/24
- [PATCH v3 05/14] RISC-V: Adding XTheadBs ISA extension, Christoph Muellner, 2023/01/24
- [PATCH v3 06/14] RISC-V: Adding XTheadCondMov ISA extension, Christoph Muellner, 2023/01/24
- [PATCH v3 07/14] RISC-V: Adding T-Head multiply-accumulate instructions, Christoph Muellner, 2023/01/24
- [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension, Christoph Muellner, 2023/01/24
  - Re: [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension, Richard Henderson, 2023/01/24
    - Re: [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension, LIU Zhiwei, 2023/01/29
    - Re: [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension, Richard Henderson <=
    - Re: [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension, LIU Zhiwei, 2023/01/30
    - Re: [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension, Richard Henderson, 2023/01/30
    - Re: [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension, LIU Zhiwei, 2023/01/30
    - Re: [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension, Christoph Müllner, 2023/01/31
- [PATCH v3 10/14] RISC-V: Adding T-Head FMemIdx extension, Christoph Muellner, 2023/01/24
- [PATCH v3 09/14] RISC-V: Adding T-Head MemIdx extension, Christoph Muellner, 2023/01/24
  - Re: [PATCH v3 09/14] RISC-V: Adding T-Head MemIdx extension, Richard Henderson, 2023/01/24
    - Re: [PATCH v3 09/14] RISC-V: Adding T-Head MemIdx extension, LIU Zhiwei, 2023/01/30
    - Re: [PATCH v3 09/14] RISC-V: Adding T-Head MemIdx extension, Christoph Müllner, 2023/01/31
- [PATCH v3 13/14] RISC-V: Adding XTheadFmv ISA extension, Christoph Muellner, 2023/01/24

Prev by Date: Re: [PATCH v8 5/5] riscv: Correctly set the device-tree entry 'mmu-type'
Next by Date: Re: [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension
Previous by thread: Re: [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension
Next by thread: Re: [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension
Index(es):
- Date
- Thread