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[PATCH v4 00/14] Add support for the T-Head vendor extensions
From: |
Christoph Muellner |
Subject: |
[PATCH v4 00/14] Add support for the T-Head vendor extensions |
Date: |
Tue, 31 Jan 2023 19:01:44 +0100 |
From: Christoph Müllner <christoph.muellner@vrull.eu>
This series introduces support for the T-Head vendor extensions,
which are implemented e.g. in the XuanTie C906 and XuanTie C910:
* XTheadBa
* XTheadBb
* XTheadBs
* XTheadCmo
* XTheadCondMov
* XTheadFMemIdx
* XTheadFmv
* XTheadMac
* XTheadMemIdx
* XTheadMemPair
* XTheadSync
The xthead* extensions are documented here:
https://github.com/T-head-Semi/thead-extension-spec/releases/latest
The "th." instruction prefix prevents future conflicts with standard
extensions and has been documentented in the RISC-V toolchain conventions:
https://github.com/riscv-non-isa/riscv-toolchain-conventions
Note, that the T-Head vendor extensions do not contain all
vendor-specific functionality of the T-Head SoCs
(e.g. no vendor-specific CSRs are included).
Instead the extensions cover coherent functionality,
that is exposed to S and U mode.
To enable the extensions above, the following two methods are possible:
* add the extension to the arch string
E.g. QEMU_CPU="any,xtheadcmo=true,xtheadsync=true"
* implicitly select the extensions via CPU selection
E.g. QEMU_CPU="thead-c906"
Major changes in v2:
- Add ISA_EXT_DATA_ENTRY()s
- Use single decoder for XThead extensions
- Simplify a lot of translation functions
- Fix RV32 behaviour
- Added XTheadFmv
- Addressed all comments of v1
Major changes in v3:
- Drop XMAE patch
- Rename priv level test macros
Changes in v4:
- Address review comments from Richard Henderson
Christoph Müllner (14):
RISC-V: Adding XTheadCmo ISA extension
RISC-V: Adding XTheadSync ISA extension
RISC-V: Adding XTheadBa ISA extension
RISC-V: Adding XTheadBb ISA extension
RISC-V: Adding XTheadBs ISA extension
RISC-V: Adding XTheadCondMov ISA extension
RISC-V: Adding T-Head multiply-accumulate instructions
RISC-V: Adding T-Head MemPair extension
RISC-V: Adding T-Head MemIdx extension
RISC-V: Adding T-Head FMemIdx extension
RISC-V: Set minimum priv version for Zfh to 1.11
RISC-V: Add initial support for T-Head C906
RISC-V: Adding XTheadFmv ISA extension
target/riscv: add a MAINTAINERS entry for XThead* extension support
MAINTAINERS | 8 +
target/riscv/cpu.c | 55 +-
target/riscv/cpu.h | 12 +
target/riscv/cpu_vendorid.h | 6 +
target/riscv/helper.h | 1 +
target/riscv/insn_trans/trans_xthead.c.inc | 1100 ++++++++++++++++++++
target/riscv/meson.build | 1 +
target/riscv/op_helper.c | 6 +
target/riscv/translate.c | 31 +
target/riscv/xthead.decode | 185 ++++
10 files changed, 1404 insertions(+), 1 deletion(-)
create mode 100644 target/riscv/cpu_vendorid.h
create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc
create mode 100644 target/riscv/xthead.decode
--
2.39.1
- [PATCH v4 00/14] Add support for the T-Head vendor extensions,
Christoph Muellner <=
- [PATCH v4 04/14] RISC-V: Adding XTheadBb ISA extension, Christoph Muellner, 2023/01/31
- [PATCH v4 07/14] RISC-V: Adding T-Head multiply-accumulate instructions, Christoph Muellner, 2023/01/31
- [PATCH v4 03/14] RISC-V: Adding XTheadBa ISA extension, Christoph Muellner, 2023/01/31
- [PATCH v4 06/14] RISC-V: Adding XTheadCondMov ISA extension, Christoph Muellner, 2023/01/31
- [PATCH v4 05/14] RISC-V: Adding XTheadBs ISA extension, Christoph Muellner, 2023/01/31
- [PATCH v4 02/14] RISC-V: Adding XTheadSync ISA extension, Christoph Muellner, 2023/01/31
- [PATCH v4 14/14] target/riscv: add a MAINTAINERS entry for XThead* extension support, Christoph Muellner, 2023/01/31
- [PATCH v4 01/14] RISC-V: Adding XTheadCmo ISA extension, Christoph Muellner, 2023/01/31
- [PATCH v4 09/14] RISC-V: Adding T-Head MemIdx extension, Christoph Muellner, 2023/01/31
- [PATCH v4 13/14] RISC-V: Adding XTheadFmv ISA extension, Christoph Muellner, 2023/01/31