Re: [PATCH 1/2] target/riscv: Add a function to refresh the dynamic CSRs xml.

[Tommy Wu]

Hi WeiWei Li,

When the CPU is realizing, it will call `riscv_gen_dynamic_csr_xml` for the first time with the correct `base_reg` value.

code flow : 

riscv_cpu_realize

→ riscv_cpu_register_gdb_regs_for_features

     → riscv_gen_dynamic_csr_xml

The functionality of `cpu->dyn_csr_base_reg` is to record the `base_reg` from

`riscv_cpu_register_gdb_regs_for_features`.

When we try to refresh the dynamic CSRs xml, we will call the function `riscv_gen_dynamic_csr_xml`

for the second time, and then we can give the correct `base_reg` value to the function

`riscv_gen_dynamic_csr_xml`, because we've record this value in the `cpu->dyn_csr_base_reg`.

Best Regards,

Tommy

On Wed, May 24, 2023 at 10:10 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:

On 2023/5/24 09:59, Tommy Wu wrote:
> Hi Weiwei Li,
>
> `dyn_csr_base_reg` will be used in `riscv_refresh_dynamic_csr_xml`
> We can initialize this variable when the cpu is realized.
I didn't find this initialization in following code.
> And used this variable in `riscv_refresh_dynamic_csr_xml`.

That's my question. In riscv_refresh_dynamic_csr_xml() ,
cpu->dyn_csr_base_reg is passed to riscv_gen_dynamic_csr_xml() as base_reg.

And then base_reg is assigned to cpu->dyn_csr_base_reg again in it. So
it's unchanged in this progress.

Another question is  dyn_csr_base_reg seems have no additional function
currently.

Regards,

Weiwei Li

>
> Best regards,
> Tommy
>
>
> On Tue, May 23, 2023 at 10:38 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
>
>     On 2023/5/23 19:44, Tommy Wu wrote:
>     > When we change the cpu extension state after the cpu is
>     > realized, we cannot print the value of some CSRs in the remote
>     > gdb debugger. The root cause is that the dynamic CSR xml is
>     > generated when the cpu is realized.
>     >
>     > This patch add a function to refresh the dynamic CSR xml after
>     > the cpu is realized.
>     >
>     > Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
>     > Reviewed-by: Frank Chang <frank.chang@sifive.com>
>     > ---
>     >   target/riscv/cpu.h     |  2 ++
>     >   target/riscv/gdbstub.c | 12 ++++++++++++
>     >   2 files changed, 14 insertions(+)
>     >
>     > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>     > index de7e43126a..dc8e592275 100644
>     > --- a/target/riscv/cpu.h
>     > +++ b/target/riscv/cpu.h
>     > @@ -494,6 +494,7 @@ struct ArchCPU {
>     >       CPUNegativeOffsetState neg;
>     >       CPURISCVState env;
>     >
>     > +    int dyn_csr_base_reg;
>
>     dyn_csr_base_reg  seems have no additional effect on the function.
>
>     And It remains unmodified in following
>     riscv_refresh_dynamic_csr_xml().
>
>     Regards,
>
>     Weiwei Li
>
>     >       char *dyn_csr_xml;
>     >       char *dyn_vreg_xml;
>     >
>     > @@ -781,6 +782,7 @@ void riscv_get_csr_ops(int csrno,
>     riscv_csr_operations *ops);
>     >   void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
>     >
>     >   void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
>     > +void riscv_refresh_dynamic_csr_xml(CPUState *cs);
>     >
>     >   uint8_t satp_mode_max_from_map(uint32_t map);
>     >   const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
>     > diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
>     > index 524bede865..9e97ee2c35 100644
>     > --- a/target/riscv/gdbstub.c
>     > +++ b/target/riscv/gdbstub.c
>     > @@ -230,6 +230,8 @@ static int
>     riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
>     >           bitsize = 64;
>     >       }
>     >
>     > +    cpu->dyn_csr_base_reg = base_reg;
>     > +
>     >       g_string_printf(s, "<?xml version=\"1.0\"?>");
>     >       g_string_append_printf(s, "<!DOCTYPE feature SYSTEM
>     \"gdb-target.dtd\">");
>     >       g_string_append_printf(s, "<feature
>     name=\"org.gnu.gdb.riscv.csr\">");
>     > @@ -349,3 +351,13 @@ void
>     riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
>     >                                    "riscv-csr.xml", 0);
>     >       }
>     >   }
>     > +
>     > +void riscv_refresh_dynamic_csr_xml(CPUState *cs)
>     > +{
>     > +    RISCVCPU *cpu = RISCV_CPU(cs);
>     > +    if (!cpu->dyn_csr_xml) {
>     > +        g_assert_not_reached();
>     > +    }
>     > +    g_free(cpu->dyn_csr_xml);
>     > +    riscv_gen_dynamic_csr_xml(cs, cpu->dyn_csr_base_reg);
>     > +}
>