Re: [PATCH v5 0/3] Smstateen FCSR

[Alistair Francis]

On Fri, May 19, 2023 at 3:51 AM Mayuresh Chitale
<mchitale@ventanamicro.com> wrote:
>
> Patch 4 and 5 of the smstateen series need to be re-submitted with
> changes described in the email below.
> https://lists.nongnu.org/archive/html/qemu-riscv/2022-11/msg00155.html
> Hence splitting the patch 4 of the original series into three and
> re-submitting along with the original patch 5.
>
> Changes in v5:
> - Ammend patch 1 commit message
> - Add reviewed-by tag
>
> Changes in v4:
> - Drop patch 3
> - Add reviewed-by tag
>
> Changes in v3:
> - Reuse TB_FLAGS.FS (instead of TB_FLAGS.HS_FS) for smstateen as HS_FS bits 
> been removed.
> - Remove fcsr check for zfh and zfhmin
>
> Changes in v2:
>  - Improve patch 1 description
>  - Reuse TB_FLAGS.HS_FS for smstateen
>  - Convert smstateen_fcsr_check to function
>  - Add fcsr check for zdinx
>
> Mayuresh Chitale (3):
>   target/riscv: smstateen check for fcsr
>   target/riscv: Reuse tb->flags.FS
>   target/riscv: smstateen knobs

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.c                      |  3 ++-
>  target/riscv/cpu_helper.c               |  6 ++++++
>  target/riscv/csr.c                      | 15 +++++++++++++++
>  target/riscv/insn_trans/trans_rvf.c.inc |  7 ++++---
>  4 files changed, 27 insertions(+), 4 deletions(-)
>
> --
> 2.34.1
>