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[PATCH 1/9] target/riscv: Use xl instead of mxl for disassemble
From: |
Christoph Muellner |
Subject: |
[PATCH 1/9] target/riscv: Use xl instead of mxl for disassemble |
Date: |
Tue, 30 May 2023 15:18:35 +0200 |
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Disassemble function(plugin_disas, target_disas, monitor_disas) will
always call set_disas_info before disassembling instructions.
plugin_disas and target_disas will always be called under a TB, which
has the same XLEN.
We can't ensure that monitor_disas will always be called under a TB,
but current XLEN will still be a better choice, thus we can ensure at
least the disassemble of the nearest one TB is right.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
target/riscv/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index db0875fb43..5b7818dbd1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -818,8 +818,9 @@ static void riscv_cpu_reset_hold(Object *obj)
static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{
RISCVCPU *cpu = RISCV_CPU(s);
+ CPURISCVState *env = &cpu->env;
- switch (riscv_cpu_mxl(&cpu->env)) {
+ switch (env->xl) {
case MXL_RV32:
info->print_insn = print_insn_riscv32;
break;
--
2.40.1
- [PATCH 0/9] disas/riscv: Add vendor extension support, Christoph Muellner, 2023/05/30
- [PATCH 1/9] target/riscv: Use xl instead of mxl for disassemble,
Christoph Muellner <=
- [PATCH 2/9] target/riscv: Factor out RISCVCPUConfig from cpu.h, Christoph Muellner, 2023/05/30
- [PATCH 5/9] disas/riscv: Encapsulate opcode_data into decode, Christoph Muellner, 2023/05/30
- [PATCH 7/9] disas/riscv: Provide infrastructure for vendor extensions, Christoph Muellner, 2023/05/30
- [PATCH 8/9] disas/riscv: Add support for XVentanaCondOps, Christoph Muellner, 2023/05/30
- [PATCH 4/9] disas/riscv: Make rv_op_illegal a shared enum value, Christoph Muellner, 2023/05/30
- [PATCH 9/9] disas/riscv: Add support for XThead* instructions, Christoph Muellner, 2023/05/30
- [PATCH 3/9] disas/riscv: Move types/constants to new header file, Christoph Muellner, 2023/05/30
- [PATCH 6/9] target/riscv/cpu: Share RISCVCPUConfig with disassembler, Christoph Muellner, 2023/05/30