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[PATCH v3 15/16] target/riscv: Restrict TCG-specific prototype declarati
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From: |
Philippe Mathieu-Daudé |
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Subject: |
[PATCH v3 15/16] target/riscv: Restrict TCG-specific prototype declarations |
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Date: |
Tue, 11 Jul 2023 14:14:52 +0200 |
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/cpu.h | 3 +++
target/riscv/cpu.c | 11 +++++++++++
2 files changed, 14 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6d78e59214..d2a9764317 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -479,7 +479,10 @@ RISCVException smstateen_acc_ok(CPURISCVState *env, int
index, uint64_t bit);
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
+#ifdef CONFIG_TCG
void riscv_translate_init(void);
+#endif
+
G_NORETURN void riscv_raise_exception(CPURISCVState *env,
uint32_t exception, uintptr_t pc);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 91433f3041..c96819daf7 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -38,7 +38,9 @@
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "fpu/softfloat-helpers.h"
+#ifdef CONFIG_TCG
#include "tcg/tcg.h"
+#endif
/* RISC-V CPU definitions */
static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
@@ -782,6 +784,7 @@ static vaddr riscv_cpu_get_pc(CPUState *cs)
return env->pc;
}
+#ifdef CONFIG_TCG
static void riscv_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
@@ -799,6 +802,7 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
}
}
}
+#endif
static bool riscv_cpu_has_work(CPUState *cs)
{
@@ -815,6 +819,7 @@ static bool riscv_cpu_has_work(CPUState *cs)
#endif
}
+#ifdef CONFIG_TCG
static void riscv_restore_state_to_opc(CPUState *cs,
const TranslationBlock *tb,
const uint64_t *data)
@@ -837,6 +842,7 @@ static void riscv_restore_state_to_opc(CPUState *cs,
}
env->bins = data[1];
}
+#endif
static void riscv_cpu_reset_hold(Object *obj)
{
@@ -1991,6 +1997,8 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
};
#endif
+#ifdef CONFIG_TCG
+
#include "hw/core/tcg-cpu-ops.h"
static const struct TCGCPUOps riscv_tcg_ops = {
@@ -2009,6 +2017,7 @@ static const struct TCGCPUOps riscv_tcg_ops = {
.debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
#endif /* !CONFIG_USER_ONLY */
};
+#endif /* CONFIG_TCG */
static bool riscv_cpu_is_dynamic(Object *cpu_obj)
{
@@ -2152,7 +2161,9 @@ static void riscv_cpu_class_init(ObjectClass *c, void
*data)
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
+#ifdef CONFIG_TCG
cc->tcg_ops = &riscv_tcg_ops;
+#endif /* CONFIG_TCG */
object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid,
cpu_set_mvendorid, NULL, NULL);
--
2.38.1
- [PATCH v3 10/16] target/riscv: Extract TCG-specific code from debug.c, (continued)
- [PATCH v3 10/16] target/riscv: Extract TCG-specific code from debug.c, Philippe Mathieu-Daudé, 2023/07/11
- [PATCH v3 09/16] target/riscv: Expose some 'trigger' prototypes from debug.c, Philippe Mathieu-Daudé, 2023/07/11
- [PATCH v3 11/16] target/riscv: Move sysemu-specific debug files to target/riscv/sysemu/, Philippe Mathieu-Daudé, 2023/07/11
- [PATCH v3 12/16] target/riscv: Expose riscv_cpu_pending_to_irq() from cpu_helper.c, Philippe Mathieu-Daudé, 2023/07/11
- [RFC PATCH v3 13/16] target/riscv: Move TCG/sysemu-specific code to tcg/sysemu/cpu_helper.c, Philippe Mathieu-Daudé, 2023/07/11
- [PATCH v3 14/16] target/riscv: Move sysemu-specific code to sysemu/cpu_helper.c, Philippe Mathieu-Daudé, 2023/07/11
- [PATCH v3 15/16] target/riscv: Restrict TCG-specific prototype declarations,
Philippe Mathieu-Daudé <=
- [PATCH v3 16/16] gitlab-ci.d/crossbuilds: Add KVM riscv64 cross-build jobs, Philippe Mathieu-Daudé, 2023/07/11