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[PATCH for-8.2 3/7] target/riscv/cpu.c: split vendor exts from riscv_cpu
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH for-8.2 3/7] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[] |
Date: |
Wed, 12 Jul 2023 16:01:45 -0300 |
Our goal is to make riscv_cpu_extensions[] hold only ratified,
non-vendor extensions.
Create a new riscv_cpu_vendor_exts[] array for them, changing
riscv_cpu_add_user_properties() accordingly.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 34 ++++++++++++++++++++--------------
1 file changed, 20 insertions(+), 14 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 735e0ed793..9bbdc46126 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1808,20 +1808,6 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false),
DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
- /* Vendor-specific custom extensions */
- DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
- DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false),
- DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
- DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
- DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
- DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false),
- DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false),
- DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false),
- DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false),
- DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false),
- DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
- DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,
false),
-
/* These are experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
@@ -1840,6 +1826,23 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_END_OF_LIST(),
};
+static Property riscv_cpu_vendor_exts[] = {
+ DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
+ DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false),
+ DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
+ DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
+ DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
+ DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false),
+ DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false),
+ DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false),
+ DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false),
+ DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false),
+ DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
+ DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,
false),
+
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static Property riscv_cpu_options[] = {
DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
@@ -1921,6 +1924,9 @@ static void riscv_cpu_add_user_properties(Object *obj)
qdev_property_add_static(dev, prop);
}
+ for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) {
+ qdev_property_add_static(dev, prop);
+ }
}
static Property riscv_cpu_properties[] = {
--
2.41.0
- [PATCH for-8.2 0/7] target/riscv: add 'max' CPU type, Daniel Henrique Barboza, 2023/07/12
- [PATCH for-8.2 1/7] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[], Daniel Henrique Barboza, 2023/07/12
- [PATCH for-8.2 2/7] target/riscv/cpu.c: skip 'bool' check when filtering KVM props, Daniel Henrique Barboza, 2023/07/12
- [PATCH for-8.2 4/7] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[], Daniel Henrique Barboza, 2023/07/12
- [PATCH for-8.2 5/7] target/riscv/cpu.c: add a ADD_CPU_PROPERTIES_ARRAY() macro, Daniel Henrique Barboza, 2023/07/12
- [PATCH for-8.2 3/7] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[],
Daniel Henrique Barboza <=
- [PATCH for-8.2 7/7] avocado, risc-v: add opensbi tests for 'max' CPU, Daniel Henrique Barboza, 2023/07/12
- [PATCH for-8.2 6/7] target/riscv: add 'max' CPU type, Daniel Henrique Barboza, 2023/07/12
- Re: [PATCH for-8.2 6/7] target/riscv: add 'max' CPU type, Conor Dooley, 2023/07/12
- Re: [PATCH for-8.2 6/7] target/riscv: add 'max' CPU type, Daniel Henrique Barboza, 2023/07/12
- Re: [PATCH for-8.2 6/7] target/riscv: add 'max' CPU type, Conor Dooley, 2023/07/12
- Re: [PATCH for-8.2 6/7] target/riscv: add 'max' CPU type, Daniel Henrique Barboza, 2023/07/12
- Re: [PATCH for-8.2 6/7] target/riscv: add 'max' CPU type, Conor Dooley, 2023/07/12
- Re: [PATCH for-8.2 6/7] target/riscv: add 'max' CPU type, Daniel Henrique Barboza, 2023/07/12
- Re: [PATCH for-8.2 6/7] target/riscv: add 'max' CPU type, Conor Dooley, 2023/07/12
- Boot failure after QEMU's upgrade to OpenSBI v1.3 (was Re: [PATCH for-8.2 6/7] target/riscv: add 'max' CPU type), Conor Dooley, 2023/07/13