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Re: [PATCH v3 07/16] target/riscv: Move TCG-specific files to target/ris
From: |
Alistair Francis |
Subject: |
Re: [PATCH v3 07/16] target/riscv: Move TCG-specific files to target/riscv/tcg/ |
Date: |
Wed, 19 Jul 2023 11:00:34 +1000 |
On Tue, Jul 11, 2023 at 10:21 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Move TCG-specific files to the a new 'tcg' sub-directory. Add
> stubs for riscv_cpu_[get/set]_fflags and riscv_raise_exception().
> Adapt meson rules.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/{ => tcg}/XVentanaCondOps.decode | 0
> target/riscv/{ => tcg}/insn16.decode | 0
> target/riscv/{ => tcg}/insn32.decode | 0
> target/riscv/{ => tcg}/xthead.decode | 0
> target/riscv/{ => tcg}/bitmanip_helper.c | 0
> target/riscv/{ => tcg}/crypto_helper.c | 0
> target/riscv/{ => tcg}/fpu_helper.c | 0
> target/riscv/{ => tcg}/m128_helper.c | 0
> target/riscv/{ => tcg}/op_helper.c | 0
> target/riscv/tcg/tcg-stub.c | 25 +++++++++++++++++++
> target/riscv/{ => tcg}/translate.c | 0
> target/riscv/{ => tcg}/vector_helper.c | 0
> target/riscv/{ => tcg}/zce_helper.c | 0
> target/riscv/meson.build | 18 +------------
> target/riscv/tcg/meson.build | 19 ++++++++++++++
> 15 files changed, 45 insertions(+), 17 deletions(-)
> rename target/riscv/{ => tcg}/XVentanaCondOps.decode (100%)
> rename target/riscv/{ => tcg}/insn16.decode (100%)
> rename target/riscv/{ => tcg}/insn32.decode (100%)
> rename target/riscv/{ => tcg}/xthead.decode (100%)
> rename target/riscv/{ => tcg}/bitmanip_helper.c (100%)
> rename target/riscv/{ => tcg}/crypto_helper.c (100%)
> rename target/riscv/{ => tcg}/fpu_helper.c (100%)
> rename target/riscv/{ => tcg}/m128_helper.c (100%)
> rename target/riscv/{ => tcg}/op_helper.c (100%)
> create mode 100644 target/riscv/tcg/tcg-stub.c
> rename target/riscv/{ => tcg}/translate.c (100%)
> rename target/riscv/{ => tcg}/vector_helper.c (100%)
> rename target/riscv/{ => tcg}/zce_helper.c (100%)
> create mode 100644 target/riscv/tcg/meson.build
>
> diff --git a/target/riscv/XVentanaCondOps.decode
> b/target/riscv/tcg/XVentanaCondOps.decode
> similarity index 100%
> rename from target/riscv/XVentanaCondOps.decode
> rename to target/riscv/tcg/XVentanaCondOps.decode
> diff --git a/target/riscv/insn16.decode b/target/riscv/tcg/insn16.decode
> similarity index 100%
> rename from target/riscv/insn16.decode
> rename to target/riscv/tcg/insn16.decode
> diff --git a/target/riscv/insn32.decode b/target/riscv/tcg/insn32.decode
> similarity index 100%
> rename from target/riscv/insn32.decode
> rename to target/riscv/tcg/insn32.decode
> diff --git a/target/riscv/xthead.decode b/target/riscv/tcg/xthead.decode
> similarity index 100%
> rename from target/riscv/xthead.decode
> rename to target/riscv/tcg/xthead.decode
> diff --git a/target/riscv/bitmanip_helper.c
> b/target/riscv/tcg/bitmanip_helper.c
> similarity index 100%
> rename from target/riscv/bitmanip_helper.c
> rename to target/riscv/tcg/bitmanip_helper.c
> diff --git a/target/riscv/crypto_helper.c b/target/riscv/tcg/crypto_helper.c
> similarity index 100%
> rename from target/riscv/crypto_helper.c
> rename to target/riscv/tcg/crypto_helper.c
> diff --git a/target/riscv/fpu_helper.c b/target/riscv/tcg/fpu_helper.c
> similarity index 100%
> rename from target/riscv/fpu_helper.c
> rename to target/riscv/tcg/fpu_helper.c
> diff --git a/target/riscv/m128_helper.c b/target/riscv/tcg/m128_helper.c
> similarity index 100%
> rename from target/riscv/m128_helper.c
> rename to target/riscv/tcg/m128_helper.c
> diff --git a/target/riscv/op_helper.c b/target/riscv/tcg/op_helper.c
> similarity index 100%
> rename from target/riscv/op_helper.c
> rename to target/riscv/tcg/op_helper.c
> diff --git a/target/riscv/tcg/tcg-stub.c b/target/riscv/tcg/tcg-stub.c
> new file mode 100644
> index 0000000000..dfe42ae2ac
> --- /dev/null
> +++ b/target/riscv/tcg/tcg-stub.c
> @@ -0,0 +1,25 @@
> +/*
> + * QEMU RISC-V TCG stubs
> + *
> + * Copyright (c) 2023 Linaro
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +#include "qemu/osdep.h"
> +#include "cpu.h"
> +
> +target_ulong riscv_cpu_get_fflags(CPURISCVState *env)
> +{
> + g_assert_not_reached();
> +}
> +
> +void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong)
> +{
> + g_assert_not_reached();
> +}
> +
> +G_NORETURN void riscv_raise_exception(CPURISCVState *env,
> + uint32_t exception, uintptr_t pc)
> +{
> + g_assert_not_reached();
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/tcg/translate.c
> similarity index 100%
> rename from target/riscv/translate.c
> rename to target/riscv/tcg/translate.c
> diff --git a/target/riscv/vector_helper.c b/target/riscv/tcg/vector_helper.c
> similarity index 100%
> rename from target/riscv/vector_helper.c
> rename to target/riscv/tcg/vector_helper.c
> diff --git a/target/riscv/zce_helper.c b/target/riscv/tcg/zce_helper.c
> similarity index 100%
> rename from target/riscv/zce_helper.c
> rename to target/riscv/tcg/zce_helper.c
> diff --git a/target/riscv/meson.build b/target/riscv/meson.build
> index 8967dfaded..8ef47f43f9 100644
> --- a/target/riscv/meson.build
> +++ b/target/riscv/meson.build
> @@ -1,34 +1,18 @@
> -# FIXME extra_args should accept files()
> -gen = [
> - decodetree.process('insn16.decode', extra_args:
> ['--static-decode=decode_insn16', '--insnwidth=16']),
> - decodetree.process('insn32.decode', extra_args:
> '--static-decode=decode_insn32'),
> - decodetree.process('xthead.decode', extra_args:
> '--static-decode=decode_xthead'),
> - decodetree.process('XVentanaCondOps.decode', extra_args:
> '--static-decode=decode_XVentanaCodeOps'),
> -]
> -
> riscv_ss = ss.source_set()
> riscv_system_ss = ss.source_set()
>
> -riscv_ss.add(gen)
> riscv_ss.add(files(
> 'cpu.c',
> 'cpu_helper.c',
> 'csr.c',
> - 'fpu_helper.c',
> 'gdbstub.c',
> - 'op_helper.c',
> - 'vector_helper.c',
> - 'bitmanip_helper.c',
> - 'translate.c',
> - 'm128_helper.c',
> - 'crypto_helper.c',
> - 'zce_helper.c'
> ))
>
> riscv_system_ss.add(files(
> 'debug.c',
> ))
>
> +subdir('tcg')
> subdir('sysemu')
>
> target_arch += {'riscv': riscv_ss}
> diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build
> new file mode 100644
> index 0000000000..65670493b1
> --- /dev/null
> +++ b/target/riscv/tcg/meson.build
> @@ -0,0 +1,19 @@
> +# FIXME extra_args should accept files()
> +gen = [
> + decodetree.process('insn16.decode', extra_args:
> ['--static-decode=decode_insn16', '--insnwidth=16']),
> + decodetree.process('insn32.decode', extra_args:
> '--static-decode=decode_insn32'),
> + decodetree.process('xthead.decode', extra_args:
> '--static-decode=decode_xthead'),
> + decodetree.process('XVentanaCondOps.decode', extra_args:
> '--static-decode=decode_XVentanaCodeOps'),
> +]
> +riscv_ss.add(when: 'CONFIG_TCG', if_true: gen)
> +
> +riscv_ss.add(when: 'CONFIG_TCG', if_true: files(
> + 'fpu_helper.c',
> + 'op_helper.c',
> + 'vector_helper.c',
> + 'bitmanip_helper.c',
> + 'translate.c',
> + 'm128_helper.c',
> + 'crypto_helper.c',
> + 'zce_helper.c',
> +), if_false: files('tcg-stub.c'))
> --
> 2.38.1
>
>
- [PATCH v3 02/16] target/riscv: Remove unused 'instmap.h' header in translate.c, (continued)
- [PATCH v3 02/16] target/riscv: Remove unused 'instmap.h' header in translate.c, Philippe Mathieu-Daudé, 2023/07/11
- [PATCH v3 03/16] target/riscv: Restrict sysemu specific header to user emulation, Philippe Mathieu-Daudé, 2023/07/11
- [PATCH v3 05/16] target/riscv: Move sysemu-specific files to target/riscv/sysemu/, Philippe Mathieu-Daudé, 2023/07/11
- [PATCH v3 04/16] target/riscv: Restrict 'rv128' machine to TCG accelerator, Philippe Mathieu-Daudé, 2023/07/11
- [PATCH v3 06/16] target/riscv: Restrict riscv_cpu_do_interrupt() to sysemu, Philippe Mathieu-Daudé, 2023/07/11
- [PATCH v3 08/16] target/riscv: Move TCG-specific cpu_get_tb_cpu_state() to tcg/cpu.c, Philippe Mathieu-Daudé, 2023/07/11
- [PATCH v3 07/16] target/riscv: Move TCG-specific files to target/riscv/tcg/, Philippe Mathieu-Daudé, 2023/07/11
- Re: [PATCH v3 07/16] target/riscv: Move TCG-specific files to target/riscv/tcg/,
Alistair Francis <=
- [PATCH v3 10/16] target/riscv: Extract TCG-specific code from debug.c, Philippe Mathieu-Daudé, 2023/07/11
- [PATCH v3 09/16] target/riscv: Expose some 'trigger' prototypes from debug.c, Philippe Mathieu-Daudé, 2023/07/11
- [PATCH v3 11/16] target/riscv: Move sysemu-specific debug files to target/riscv/sysemu/, Philippe Mathieu-Daudé, 2023/07/11
- [PATCH v3 12/16] target/riscv: Expose riscv_cpu_pending_to_irq() from cpu_helper.c, Philippe Mathieu-Daudé, 2023/07/11
- [RFC PATCH v3 13/16] target/riscv: Move TCG/sysemu-specific code to tcg/sysemu/cpu_helper.c, Philippe Mathieu-Daudé, 2023/07/11
- [PATCH v3 14/16] target/riscv: Move sysemu-specific code to sysemu/cpu_helper.c, Philippe Mathieu-Daudé, 2023/07/11