Re: [RFC] risc-v vector (RVV) emulation performance issues

[Philippe Mathieu-Daudé]

On 24/7/23 15:40, Daniel Henrique Barboza wrote:
> Hi,
>
> As some of you are already aware the current RVV emulation could be faster.
> We have at least one commit (bc0ec52eb2, "target/riscv/vector_helper.c:
> skip set tail when vta is zero") that tried to address at least part of the
> problem.


> First thing that caught my attention is vext_ldst_us from 
> target/riscv/vector_helper.c:
>
>      /* load bytes from guest memory */
>      for (i = env->vstart; i < evl; i++, env->vstart++) {
>          k = 0;
>          while (k < nf) {
>              target_ulong addr = base + ((i * nf + k) << log2_esz);
>              ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, 
> vd, ra);
>              k++;
>          }
>      }
>      env->vstart = 0;
>
> Given that this is a unit-stride load that access contiguous elements in 
> memory it
> seems that this loop could be optimized/removed since it's 
> loading/storing bytes
> one by one. I didn't find any TCG op to do that though. I assume that 
> ARM SVE might
> have something of the sorts. Richard, care to comment?

Have you looked at the "tcg/tcg-op-gvec-common.h" API?