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Re: [PATCH 04/10] hw/riscv: virt: Add PCIe HIGHMEM in memmap
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From: |
Sunil V L |
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Subject: |
Re: [PATCH 04/10] hw/riscv: virt: Add PCIe HIGHMEM in memmap |
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Date: |
Thu, 27 Jul 2023 16:29:19 +0530 |
On Mon, Jul 24, 2023 at 05:32:54PM +0200, Igor Mammedov wrote:
> On Wed, 12 Jul 2023 22:09:37 +0530
> Sunil V L <sunilvl@ventanamicro.com> wrote:
>
> > PCIe High MMIO base is actually dynamic and fixed at
> > run time based on the RAM configured. Currently, this is
> > not part of the memmap and kept in separate static variable
> > in virt.c. However, ACPI code also needs this information
> > to populate DSDT. So, once the base is discovered, merge
> > this into the final memmap which can be used to create
> > ACPI tables later.
>
> can ACPI code fetch virt_high_pcie_memmap at runtime from
> host bridge (like we do in pc/q35)?
>
Hi Igor,
Looking at the current design of virt machines (arm/loongarch/riscv),
getting this directly from the memmap looks simpler. ARM ACPI also uses
the memmap to get the pcie_high space. It appears to me we need some
more infrastructure code if ACPI needs to fetch from host bridge. I am
not sure why that would be beneficial.
Thanks,
Sunil
- [PATCH 02/10] hw/riscv: virt: Add PCI bus reference in RISCVVirtState, (continued)
[PATCH 05/10] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC, Sunil V L, 2023/07/12
[PATCH 06/10] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT, Sunil V L, 2023/07/12
[PATCH 07/10] hw/riscv/virt-acpi-build.c: Add APLIC in the MADT, Sunil V L, 2023/07/12
[PATCH 09/10] hw/riscv/virt-acpi-build.c: Add MMU node in RHCT, Sunil V L, 2023/07/12