Re: [PATCH] target/riscv: Align the AIA model to v1.0 ratified spec

[Alistair Francis]

On Wed, Aug 16, 2023 at 4:18 PM Tommy Wu <tommy.wu@sifive.com> wrote:
>
> According to the new spec, when vsiselect has a reserved value, attempts
> from M-mode or HS-mode to access vsireg, or from VS-mode to access
> sireg, should preferably raise an illegal instruction exception.
>
> Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  target/riscv/csr.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index ea7585329e..e4244b8dac 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1685,7 +1685,7 @@ static int rmw_iprio(target_ulong xlen,
>  static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val,
>                       target_ulong new_val, target_ulong wr_mask)
>  {
> -    bool virt;
> +    bool virt, isel_reserved;
>      uint8_t *iprio;
>      int ret = -EINVAL;
>      target_ulong priv, isel, vgein;
> @@ -1695,6 +1695,7 @@ static int rmw_xireg(CPURISCVState *env, int csrno, 
> target_ulong *val,
>
>      /* Decode register details from CSR number */
>      virt = false;
> +    isel_reserved = false;
>      switch (csrno) {
>      case CSR_MIREG:
>          iprio = env->miprio;
> @@ -1739,11 +1740,13 @@ static int rmw_xireg(CPURISCVState *env, int csrno, 
> target_ulong *val,
>                                                    riscv_cpu_mxl_bits(env)),
>                                      val, new_val, wr_mask);
>          }
> +    } else {
> +        isel_reserved = true;
>      }
>
>  done:
>      if (ret) {
> -        return (env->virt_enabled && virt) ?
> +        return (env->virt_enabled && virt && !isel_reserved) ?
>                 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
>      }
>      return RISCV_EXCP_NONE;
> --
> 2.27.0
>
>