Re: [PATCH v9 00/20] riscv: 'max' CPU, detect user choice in TCG

[Alistair Francis]

On Sat, Sep 2, 2023 at 5:48 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Hi,
>
> This new version contains suggestions made by Andrew Jones in v8.
>
> Most notable change is the removal of the opensbi.py test in patch 11,
> which was replaced by a TuxBoot test. It's more suitable to test the
> integrity of all the extensions enabled by the 'max' CPU.
>
> The series is available in this branch:
>
> https://gitlab.com/danielhb/qemu/-/tree/max_cpu_user_choice_v9
>
> Patches missing acks: 11, 15
>
> Changes from v8:
> - patch 7:
>   - add g_assert(array) at the start of riscv_cpu_add_qdev_prop_array()
> - patch 8:
>   - add g_assert(array) at the start of riscv_cpu_add_kvm_unavail_prop_array()
> - patch 11:
>   - removed both opensbi.py tests
>   - added 2 'max' cpu tuxboot tests in tuxrun_baselines.py
> - patch 12:
>   - fixed typos in deprecated.rst
> - patch 15:
>   - use g_assert_not_reached() at the end of cpu_cfg_ext_get_min_version()
> - patch 19:
>   - added comment on top of riscv_cpu_add_misa_properties() explaining why
>     we're not implementing user choice support for MISA properties
> - patch 20:
>   - warn_report() is now called after the G error conditions
> - v8 link: 
> https://lore.kernel.org/qemu-riscv/20230824221440.484675-1-dbarboza@ventanamicro.com/
>
>
>
> Daniel Henrique Barboza (20):
>   target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
>   target/riscv/cpu.c: skip 'bool' check when filtering KVM props
>   target/riscv/cpu.c: split kvm prop handling to its own helper
>   target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[]
>   target/riscv/cpu.c: split non-ratified exts from
>     riscv_cpu_extensions[]
>   target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[]
>   target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array()
>   target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array()
>   target/riscv/cpu.c: limit cfg->vext_spec log message
>   target/riscv: add 'max' CPU type
>   avocado, risc-v: add tuxboot tests for 'max' CPU
>   target/riscv: deprecate the 'any' CPU type
>   target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled
>   target/riscv: make CPUCFG() macro public
>   target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update()
>   target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize()
>   target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig
>   target/riscv: use isa_ext_update_enabled() in
>     init_max_cpu_extensions()
>   target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update()
>   target/riscv/cpu.c: consider user option with RVG

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  docs/about/deprecated.rst         |  12 +
>  target/riscv/cpu-qom.h            |   1 +
>  target/riscv/cpu.c                | 564 +++++++++++++++++++++---------
>  target/riscv/cpu.h                |   2 +
>  target/riscv/kvm.c                |   8 +-
>  tests/avocado/tuxrun_baselines.py |  32 ++
>  6 files changed, 450 insertions(+), 169 deletions(-)
>
> --
> 2.41.0
>
>