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[PATCH v10 20/20] target/riscv/cpu.c: consider user option with RVG
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From: |
Daniel Henrique Barboza |
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Subject: |
[PATCH v10 20/20] target/riscv/cpu.c: consider user option with RVG |
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Date: |
Tue, 12 Sep 2023 10:24:23 -0300 |
Enabling RVG will enable a set of extensions that we're not checking if
the user was okay enabling or not. And in this case we want to error
out, instead of ignoring, otherwise we will be inconsistent enabling RVG
without all its extensions.
After this patch, disabling ifencei or icsr while enabling RVG will
result in error:
$ ./build/qemu-system-riscv64 -M virt -cpu rv64,g=true,Zifencei=false
--nographic
qemu-system-riscv64: RVG requires Zifencei but user set Zifencei to false
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/cpu.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fb8e4d6a8f..2644638b11 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1153,9 +1153,23 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
Error **errp)
riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
riscv_has_ext(env, RVD) &&
cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
+
+ if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
+ !cpu->cfg.ext_icsr) {
+ error_setg(errp, "RVG requires Zicsr but user set Zicsr to false");
+ return;
+ }
+
+ if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) &&
+ !cpu->cfg.ext_ifencei) {
+ error_setg(errp, "RVG requires Zifencei but user set "
+ "Zifencei to false");
+ return;
+ }
+
warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
- cpu->cfg.ext_icsr = true;
- cpu->cfg.ext_ifencei = true;
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
--
2.41.0
- [PATCH v10 10/20] target/riscv: add 'max' CPU type, (continued)
- [PATCH v10 10/20] target/riscv: add 'max' CPU type, Daniel Henrique Barboza, 2023/09/12
- [PATCH v10 13/20] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled, Daniel Henrique Barboza, 2023/09/12
- [PATCH v10 12/20] target/riscv: deprecate the 'any' CPU type, Daniel Henrique Barboza, 2023/09/12
- [PATCH v10 14/20] target/riscv: make CPUCFG() macro public, Daniel Henrique Barboza, 2023/09/12
- [PATCH v10 11/20] avocado, risc-v: add tuxboot tests for 'max' CPU, Daniel Henrique Barboza, 2023/09/12
- [PATCH v10 16/20] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize(), Daniel Henrique Barboza, 2023/09/12
- [PATCH v10 18/20] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions(), Daniel Henrique Barboza, 2023/09/12
- [PATCH v10 15/20] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update(), Daniel Henrique Barboza, 2023/09/12
- [PATCH v10 19/20] target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update(), Daniel Henrique Barboza, 2023/09/12
- [PATCH v10 17/20] target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig, Daniel Henrique Barboza, 2023/09/12
- [PATCH v10 20/20] target/riscv/cpu.c: consider user option with RVG,
Daniel Henrique Barboza <=
- Re: [PATCH v10 00/20] riscv: 'max' CPU, detect user choice in TCG, Alistair Francis, 2023/09/17