Re: [RFC v1 2/8] target/riscv: Add new S{sn, mn, m}jpm extensions as part of Zjpm v0.6.1

[Alistair Francis]

On Sat, Sep 9, 2023 at 4:28 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
> ---
>  target/riscv/cpu.c     | 7 +++++++
>  target/riscv/cpu_cfg.h | 3 +++
>  target/riscv/machine.c | 6 ++++--
>  3 files changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index f937820976..af8f16b94f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -137,6 +137,9 @@ static const struct isa_ext_data isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
>      ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
>      ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
> +    ISA_EXT_DATA_ENTRY(ssnjpm, PRIV_VERSION_1_12_0, ext_ssnjpm),
> +    ISA_EXT_DATA_ENTRY(smnjpm, PRIV_VERSION_1_12_0, ext_smnjpm),
> +    ISA_EXT_DATA_ENTRY(smmjpm, PRIV_VERSION_1_12_0, ext_smmjpm),
>      ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
>      ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
>      ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
> @@ -1796,6 +1799,10 @@ static Property riscv_cpu_extensions[] = {
>      DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
>
>      DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
> +    /* Zjpm v0.6.1 extensions */
> +    DEFINE_PROP_BOOL("ssnjpm", RISCVCPU, cfg.ext_ssnjpm, false),
> +    DEFINE_PROP_BOOL("smnjpm", RISCVCPU, cfg.ext_smnjpm, false),
> +    DEFINE_PROP_BOOL("smmjpm", RISCVCPU, cfg.ext_smmjpm, false),

This will be exposed to users, so they can enable these extensions
after this patch is applied. I'm guessing the future patches in the
series will actually add support, so this change should be split out
to the last patch.

Alistair

>
>      DEFINE_PROP_BOOL("zca", RISCVCPU, cfg.ext_zca, false),
>      DEFINE_PROP_BOOL("zcb", RISCVCPU, cfg.ext_zcb, false),
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index 2bd9510ba3..9e9eb7cd1d 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -93,6 +93,9 @@ struct RISCVCPUConfig {
>      bool ext_smaia;
>      bool ext_ssaia;
>      bool ext_sscofpmf;
> +    bool ext_ssnjpm;
> +    bool ext_smnjpm;
> +    bool ext_smmjpm;
>      bool rvv_ta_all_1s;
>      bool rvv_ma_all_1s;
>
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 8b1a109275..d50ff5421f 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -150,9 +150,8 @@ static const VMStateDescription vmstate_vector = {
>  static bool pointermasking_needed(void *opaque)
>  {
>      RISCVCPU *cpu = opaque;
> -    CPURISCVState *env = &cpu->env;
>
> -    return riscv_has_ext(env, RVJ);
> +    return cpu->cfg.ext_ssnjpm || cpu->cfg.ext_smnjpm || cpu->cfg.ext_smmjpm;
>  }
>
>  static const VMStateDescription vmstate_pointermasking = {
> @@ -161,6 +160,9 @@ static const VMStateDescription vmstate_pointermasking = {
>      .minimum_version_id = 1,
>      .needed = pointermasking_needed,
>      .fields = (VMStateField[]) {
> +        VMSTATE_UINTTL(env.mseccfg, RISCVCPU),
> +        VMSTATE_UINTTL(env.senvcfg, RISCVCPU),
> +        VMSTATE_UINTTL(env.menvcfg, RISCVCPU),
>          VMSTATE_END_OF_LIST()
>      }
>  };
> --
> 2.34.1
>
>