[PATCH v3 05/19] target/riscv/cpu.c: add .instance_post

qemu-riscv

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[PATCH v3 05/19] target/riscv/cpu.c: add .instance_post_init()

From:	Daniel Henrique Barboza
Subject:	[PATCH v3 05/19] target/riscv/cpu.c: add .instance_post_init()
Date:	Wed, 20 Sep 2023 08:20:06 -0300

All generic CPUs call riscv_cpu_add_user_properties(). The 'max' CPU
calls riscv_init_max_cpu_extensions(). Both can be moved to a common
instance_post_init() callback, implemented in riscv_cpu_post_init(),
called by all CPUs. The call order then becomes:

riscv_cpu_init() -> cpu_init() of each CPU -> .instance_post_init()

In the near future riscv_cpu_post_init() will call the init() function
of the current accelerator, providing a hook for KVM and TCG accel
classes to change the init() process of the CPU.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
 target/riscv/cpu.c | 43 ++++++++++++++++++++++++++++++++-----------
 1 file changed, 32 insertions(+), 11 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9426b3b9d6..848b58e7c4 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -427,8 +427,6 @@ static void riscv_max_cpu_init(Object *obj)
     mlx = MXL_RV32;
 #endif
     set_misa(env, mlx, 0);
-    riscv_cpu_add_user_properties(obj);
-    riscv_init_max_cpu_extensions(obj);
     env->priv_ver = PRIV_VERSION_LATEST;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
@@ -442,7 +440,6 @@ static void rv64_base_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     /* We set this in the realise function */
     set_misa(env, MXL_RV64, 0);
-    riscv_cpu_add_user_properties(obj);
     /* Set latest version of privileged specification */
     env->priv_ver = PRIV_VERSION_LATEST;
 #ifndef CONFIG_USER_ONLY
@@ -566,7 +563,6 @@ static void rv128_base_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     /* We set this in the realise function */
     set_misa(env, MXL_RV128, 0);
-    riscv_cpu_add_user_properties(obj);
     /* Set latest version of privileged specification */
     env->priv_ver = PRIV_VERSION_LATEST;
 #ifndef CONFIG_USER_ONLY
@@ -579,7 +575,6 @@ static void rv32_base_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     /* We set this in the realise function */
     set_misa(env, MXL_RV32, 0);
-    riscv_cpu_add_user_properties(obj);
     /* Set latest version of privileged specification */
     env->priv_ver = PRIV_VERSION_LATEST;
 #ifndef CONFIG_USER_ONLY
@@ -666,7 +661,6 @@ static void riscv_host_cpu_init(Object *obj)
 #elif defined(TARGET_RISCV64)
     set_misa(env, MXL_RV64, 0);
 #endif
-    riscv_cpu_add_user_properties(obj);
 }
 #endif /* CONFIG_KVM */
 
@@ -1215,6 +1209,37 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int 
level)
 }
 #endif /* CONFIG_USER_ONLY */
 
+static bool riscv_cpu_is_dynamic(Object *cpu_obj)
+{
+    return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
+}
+
+static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
+{
+    return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
+}
+
+static bool riscv_cpu_has_user_properties(Object *cpu_obj)
+{
+    if (kvm_enabled() &&
+        object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) != NULL) {
+        return true;
+    }
+
+    return riscv_cpu_is_dynamic(cpu_obj);
+}
+
+static void riscv_cpu_post_init(Object *obj)
+{
+    if (riscv_cpu_has_user_properties(obj)) {
+        riscv_cpu_add_user_properties(obj);
+    }
+
+    if (riscv_cpu_has_max_extensions(obj)) {
+        riscv_init_max_cpu_extensions(obj);
+    }
+}
+
 static void riscv_cpu_init(Object *obj)
 {
     RISCVCPU *cpu = RISCV_CPU(obj);
@@ -1768,11 +1793,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
 };
 #endif
 
-static bool riscv_cpu_is_dynamic(Object *cpu_obj)
-{
-    return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
-}
-
 static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name,
                               void *opaque, Error **errp)
 {
@@ -2009,6 +2029,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
         .instance_size = sizeof(RISCVCPU),
         .instance_align = __alignof__(RISCVCPU),
         .instance_init = riscv_cpu_init,
+        .instance_post_init = riscv_cpu_post_init,
         .abstract = true,
         .class_size = sizeof(RISCVCPUClass),
         .class_init = riscv_cpu_class_init,
-- 
2.41.0

[Prev in Thread]

Current Thread

[Next in Thread]

[PATCH v3 01/19] target/riscv: introduce TCG AccelCPUClass, (continued)
- [PATCH v3 01/19] target/riscv: introduce TCG AccelCPUClass, Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 01/19] target/riscv: introduce TCG AccelCPUClass, Alistair Francis, 2023/09/22
- [PATCH v3 02/19] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn(), Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 02/19] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn(), Alistair Francis, 2023/09/22
    - Re: [PATCH v3 02/19] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn(), Daniel Henrique Barboza, 2023/09/25
    - Re: [PATCH v3 02/19] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn(), Alistair Francis, 2023/09/25
- [PATCH v3 03/19] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c, Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 03/19] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c, Alistair Francis, 2023/09/22
- [PATCH v3 04/19] target/riscv: move riscv_tcg_ops to tcg-cpu.c, Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 04/19] target/riscv: move riscv_tcg_ops to tcg-cpu.c, Alistair Francis, 2023/09/22
- [PATCH v3 05/19] target/riscv/cpu.c: add .instance_post_init(), Daniel Henrique Barboza <=
  - Re: [PATCH v3 05/19] target/riscv/cpu.c: add .instance_post_init(), Alistair Francis, 2023/09/22
- [PATCH v3 06/19] target/riscv: move 'host' CPU declaration to kvm.c, Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 06/19] target/riscv: move 'host' CPU declaration to kvm.c, Alistair Francis, 2023/09/22
- [PATCH v3 07/19] target/riscv/cpu.c: mark extensions arrays as 'const', Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 07/19] target/riscv/cpu.c: mark extensions arrays as 'const', Alistair Francis, 2023/09/22
- [PATCH v3 08/19] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c, Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 08/19] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c, Alistair Francis, 2023/09/22
- [PATCH v3 09/19] target/riscv: make riscv_add_satp_mode_properties() public, Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 09/19] target/riscv: make riscv_add_satp_mode_properties() public, Alistair Francis, 2023/09/22
- [PATCH v3 10/19] target/riscv: remove kvm-stub.c, Daniel Henrique Barboza, 2023/09/20

Prev by Date: [PATCH v3 04/19] target/riscv: move riscv_tcg_ops to tcg-cpu.c
Next by Date: [PATCH v3 06/19] target/riscv: move 'host' CPU declaration to kvm.c
Previous by thread: Re: [PATCH v3 04/19] target/riscv: move riscv_tcg_ops to tcg-cpu.c
Next by thread: Re: [PATCH v3 05/19] target/riscv/cpu.c: add .instance_post_init()
Index(es):
- Date
- Thread