[PATCH v3 07/19] target/riscv/cpu.c: mark extensions arrays as 'const'

qemu-riscv

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[PATCH v3 07/19] target/riscv/cpu.c: mark extensions arrays as 'const'

From:	Daniel Henrique Barboza
Subject:	[PATCH v3 07/19] target/riscv/cpu.c: mark extensions arrays as 'const'
Date:	Wed, 20 Sep 2023 08:20:08 -0300

We'll need to export these arrays to the accelerator classes in the next
patches. Mark them as 'const' now because they should not be modified at
runtime.

Note that 'riscv_cpu_options' will also be exported, but can't be marked
as 'const', because the properties are changed via
qdev_property_add_static().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
 target/riscv/cpu.c | 22 +++++++++++++---------
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f8368ce274..048a2dbc77 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1407,7 +1407,7 @@ typedef struct RISCVCPUMultiExtConfig {
     {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
      .enabled = _defval}
 
-static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
+static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     /* Defaults for standard extensions */
     MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
     MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
@@ -1469,7 +1469,7 @@ static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
-static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
+static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
     MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
     MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
     MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
@@ -1487,7 +1487,7 @@ static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
 };
 
 /* These are experimental so mark with 'x-' */
-static RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
+static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
     /* ePMP 0.9.3 */
     MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
     MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
@@ -1558,7 +1558,7 @@ static void cpu_get_multi_ext_cfg(Object *obj, Visitor 
*v, const char *name,
 }
 
 static void cpu_add_multi_ext_prop(Object *cpu_obj,
-                                   RISCVCPUMultiExtConfig *multi_cfg)
+                                   const RISCVCPUMultiExtConfig *multi_cfg)
 {
     object_property_add(cpu_obj, multi_cfg->name, "bool",
                         cpu_get_multi_ext_cfg,
@@ -1575,11 +1575,13 @@ static void cpu_add_multi_ext_prop(Object *cpu_obj,
 }
 
 static void riscv_cpu_add_multiext_prop_array(Object *obj,
-                                              RISCVCPUMultiExtConfig *array)
+                                        const RISCVCPUMultiExtConfig *array)
 {
+    const RISCVCPUMultiExtConfig *prop;
+
     g_assert(array);
 
-    for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
+    for (prop = array; prop && prop->name; prop++) {
         cpu_add_multi_ext_prop(obj, prop);
     }
 }
@@ -1620,11 +1622,13 @@ static void riscv_cpu_add_kvm_unavail_prop(Object *obj, 
const char *prop_name)
 }
 
 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
-                                                 RISCVCPUMultiExtConfig *array)
+                                        const RISCVCPUMultiExtConfig *array)
 {
+    const RISCVCPUMultiExtConfig *prop;
+
     g_assert(array);
 
-    for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
+    for (prop = array; prop && prop->name; prop++) {
         riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
     }
 }
@@ -1687,7 +1691,7 @@ static void riscv_init_max_cpu_extensions(Object *obj)
 {
     RISCVCPU *cpu = RISCV_CPU(obj);
     CPURISCVState *env = &cpu->env;
-    RISCVCPUMultiExtConfig *prop;
+    const RISCVCPUMultiExtConfig *prop;
 
     /* Enable RVG, RVJ and RVV that are disabled by default */
     set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
-- 
2.41.0

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Re: [PATCH v3 02/19] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn(), (continued)
- [PATCH v3 03/19] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c, Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 03/19] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c, Alistair Francis, 2023/09/22
- [PATCH v3 04/19] target/riscv: move riscv_tcg_ops to tcg-cpu.c, Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 04/19] target/riscv: move riscv_tcg_ops to tcg-cpu.c, Alistair Francis, 2023/09/22
- [PATCH v3 05/19] target/riscv/cpu.c: add .instance_post_init(), Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 05/19] target/riscv/cpu.c: add .instance_post_init(), Alistair Francis, 2023/09/22
- [PATCH v3 06/19] target/riscv: move 'host' CPU declaration to kvm.c, Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 06/19] target/riscv: move 'host' CPU declaration to kvm.c, Alistair Francis, 2023/09/22
- [PATCH v3 07/19] target/riscv/cpu.c: mark extensions arrays as 'const', Daniel Henrique Barboza <=
  - Re: [PATCH v3 07/19] target/riscv/cpu.c: mark extensions arrays as 'const', Alistair Francis, 2023/09/22
- [PATCH v3 08/19] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c, Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 08/19] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c, Alistair Francis, 2023/09/22
- [PATCH v3 09/19] target/riscv: make riscv_add_satp_mode_properties() public, Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 09/19] target/riscv: make riscv_add_satp_mode_properties() public, Alistair Francis, 2023/09/22
- [PATCH v3 10/19] target/riscv: remove kvm-stub.c, Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 10/19] target/riscv: remove kvm-stub.c, Alistair Francis, 2023/09/22
- [PATCH v3 11/19] target/riscv: introduce KVM AccelCPUClass, Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 11/19] target/riscv: introduce KVM AccelCPUClass, Alistair Francis, 2023/09/22
- [PATCH v3 12/19] target/riscv: move KVM only files to kvm subdir, Daniel Henrique Barboza, 2023/09/20

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