Re: [PATCH v3 14/19] target/riscv/cpu.c: export set

qemu-riscv

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Re: [PATCH v3 14/19] target/riscv/cpu.c: export set_misa()

From:	Alistair Francis
Subject:	Re: [PATCH v3 14/19] target/riscv/cpu.c: export set_misa()
Date:	Mon, 25 Sep 2023 11:36:11 +1000

On Wed, Sep 20, 2023 at 9:23 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> We'll move riscv_init_max_cpu_extensions() to tcg-cpu.c in the next
> patch and set_misa() needs to be usable from there.
>
> Rename it to riscv_cpu_set_misa() and make it public.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 34 ++++++++++++++++++----------------
>  target/riscv/cpu.h |  1 +
>  2 files changed, 19 insertions(+), 16 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 665c21af6a..cf191d576e 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -294,7 +294,7 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, 
> bool async)
>      }
>  }
>
> -static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
> +void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
>  {
>      env->misa_mxl_max = env->misa_mxl = mxl;
>      env->misa_ext_mask = env->misa_ext = ext;
> @@ -399,9 +399,9 @@ static void riscv_any_cpu_init(Object *obj)
>      RISCVCPU *cpu = RISCV_CPU(obj);
>      CPURISCVState *env = &cpu->env;
>  #if defined(TARGET_RISCV32)
> -    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
> +    riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | 
> RVU);
>  #elif defined(TARGET_RISCV64)
> -    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
> +    riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | 
> RVU);
>  #endif
>
>  #ifndef CONFIG_USER_ONLY
> @@ -428,7 +428,7 @@ static void riscv_max_cpu_init(Object *obj)
>  #ifdef TARGET_RISCV32
>      mlx = MXL_RV32;
>  #endif
> -    set_misa(env, mlx, 0);
> +    riscv_cpu_set_misa(env, mlx, 0);
>      env->priv_ver = PRIV_VERSION_LATEST;
>  #ifndef CONFIG_USER_ONLY
>      set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
> @@ -441,7 +441,7 @@ static void rv64_base_cpu_init(Object *obj)
>  {
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
>      /* We set this in the realise function */
> -    set_misa(env, MXL_RV64, 0);
> +    riscv_cpu_set_misa(env, MXL_RV64, 0);
>      /* Set latest version of privileged specification */
>      env->priv_ver = PRIV_VERSION_LATEST;
>  #ifndef CONFIG_USER_ONLY
> @@ -453,7 +453,8 @@ static void rv64_sifive_u_cpu_init(Object *obj)
>  {
>      RISCVCPU *cpu = RISCV_CPU(obj);
>      CPURISCVState *env = &cpu->env;
> -    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> +    riscv_cpu_set_misa(env, MXL_RV64,
> +                       RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
>      env->priv_ver = PRIV_VERSION_1_10_0;
>  #ifndef CONFIG_USER_ONLY
>      set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
> @@ -471,7 +472,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
>      RISCVCPU *cpu = RISCV_CPU(obj);
>
> -    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
> +    riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
>      env->priv_ver = PRIV_VERSION_1_10_0;
>  #ifndef CONFIG_USER_ONLY
>      set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> @@ -488,7 +489,7 @@ static void rv64_thead_c906_cpu_init(Object *obj)
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
>      RISCVCPU *cpu = RISCV_CPU(obj);
>
> -    set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
> +    riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
>      env->priv_ver = PRIV_VERSION_1_11_0;
>
>      cpu->cfg.ext_zfa = true;
> @@ -519,7 +520,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
>      RISCVCPU *cpu = RISCV_CPU(obj);
>
> -    set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
> +    riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
>      env->priv_ver = PRIV_VERSION_1_12_0;
>
>      /* Enable ISA extensions */
> @@ -564,7 +565,7 @@ static void rv128_base_cpu_init(Object *obj)
>      }
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
>      /* We set this in the realise function */
> -    set_misa(env, MXL_RV128, 0);
> +    riscv_cpu_set_misa(env, MXL_RV128, 0);
>      /* Set latest version of privileged specification */
>      env->priv_ver = PRIV_VERSION_LATEST;
>  #ifndef CONFIG_USER_ONLY
> @@ -576,7 +577,7 @@ static void rv32_base_cpu_init(Object *obj)
>  {
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
>      /* We set this in the realise function */
> -    set_misa(env, MXL_RV32, 0);
> +    riscv_cpu_set_misa(env, MXL_RV32, 0);
>      /* Set latest version of privileged specification */
>      env->priv_ver = PRIV_VERSION_LATEST;
>  #ifndef CONFIG_USER_ONLY
> @@ -588,7 +589,8 @@ static void rv32_sifive_u_cpu_init(Object *obj)
>  {
>      RISCVCPU *cpu = RISCV_CPU(obj);
>      CPURISCVState *env = &cpu->env;
> -    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> +    riscv_cpu_set_misa(env, MXL_RV32,
> +                       RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
>      env->priv_ver = PRIV_VERSION_1_10_0;
>  #ifndef CONFIG_USER_ONLY
>      set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
> @@ -606,7 +608,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
>      RISCVCPU *cpu = RISCV_CPU(obj);
>
> -    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
> +    riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
>      env->priv_ver = PRIV_VERSION_1_10_0;
>  #ifndef CONFIG_USER_ONLY
>      set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> @@ -623,7 +625,7 @@ static void rv32_ibex_cpu_init(Object *obj)
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
>      RISCVCPU *cpu = RISCV_CPU(obj);
>
> -    set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
> +    riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
>      env->priv_ver = PRIV_VERSION_1_11_0;
>  #ifndef CONFIG_USER_ONLY
>      set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> @@ -641,7 +643,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
>      RISCVCPU *cpu = RISCV_CPU(obj);
>
> -    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
> +    riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
>      env->priv_ver = PRIV_VERSION_1_10_0;
>  #ifndef CONFIG_USER_ONLY
>      set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> @@ -1618,7 +1620,7 @@ static void riscv_init_max_cpu_extensions(Object *obj)
>      const RISCVCPUMultiExtConfig *prop;
>
>      /* Enable RVG, RVJ and RVV that are disabled by default */
> -    set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
> +    riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
>
>      for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
>          isa_ext_update_enabled(cpu, prop->offset, true);
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7235eafc1a..9ec0805596 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -713,6 +713,7 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t 
> ext_offset, bool en);
>  bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
>  bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
>  int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
> +void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
>  void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
>
>  typedef struct RISCVCPUMultiExtConfig {
> --
> 2.41.0
>
>

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Re: [PATCH v3 09/19] target/riscv: make riscv_add_satp_mode_properties() public, (continued)
- [PATCH v3 10/19] target/riscv: remove kvm-stub.c, Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 10/19] target/riscv: remove kvm-stub.c, Alistair Francis, 2023/09/22
- [PATCH v3 11/19] target/riscv: introduce KVM AccelCPUClass, Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 11/19] target/riscv: introduce KVM AccelCPUClass, Alistair Francis, 2023/09/22
- [PATCH v3 12/19] target/riscv: move KVM only files to kvm subdir, Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 12/19] target/riscv: move KVM only files to kvm subdir, Alistair Francis, 2023/09/24
- [PATCH v3 13/19] target/riscv/kvm: do not use riscv_cpu_add_misa_properties(), Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 13/19] target/riscv/kvm: do not use riscv_cpu_add_misa_properties(), Alistair Francis, 2023/09/24
- [PATCH v3 14/19] target/riscv/cpu.c: export set_misa(), Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 14/19] target/riscv/cpu.c: export set_misa(), Alistair Francis <=
- [PATCH v3 15/19] target/riscv/tcg: introduce tcg_cpu_instance_init(), Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 15/19] target/riscv/tcg: introduce tcg_cpu_instance_init(), Alistair Francis, 2023/09/24
- [PATCH v3 16/19] target/riscv/cpu.c: make misa_ext_cfgs[] 'const', Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 16/19] target/riscv/cpu.c: make misa_ext_cfgs[] 'const', Alistair Francis, 2023/09/24
- [PATCH v3 17/19] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c, Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 17/19] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c, Alistair Francis, 2023/09/24
- [PATCH v3 18/19] target/riscv/cpu.c: export isa_edata_arr[], Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 18/19] target/riscv/cpu.c: export isa_edata_arr[], Alistair Francis, 2023/09/24
- [PATCH v3 19/19] target/riscv/cpu: move priv spec functions to tcg-cpu.c, Daniel Henrique Barboza, 2023/09/20
  - Re: [PATCH v3 19/19] target/riscv/cpu: move priv spec functions to tcg-cpu.c, Philippe Mathieu-Daudé, 2023/09/22

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