Re: [PATCH v3 18/19] target/riscv/cpu.c: export isa_edata_arr[]

[Alistair Francis]

On Wed, Sep 20, 2023 at 9:23 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> This array will be read by the TCG accel class, allowing it to handle
> priv spec verifications on its own. The array will remain here in cpu.c
> because it's also used by the riscv,isa string function.
>
> To export it we'll finish it with an empty element since ARRAY_SIZE()
> won't work outside of cpu.c. Get rid of its ARRAY_SIZE() usage now to
> alleviate the changes for the next patch.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 47 +++++++++++++++++++++-------------------------
>  target/riscv/cpu.h |  7 +++++++
>  2 files changed, 28 insertions(+), 26 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 46263e55d5..e97ba3df93 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -41,15 +41,6 @@ static const char riscv_single_letter_exts[] = 
> "IEMAFDQCPVH";
>  const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
>                                RVC, RVS, RVU, RVH, RVJ, RVG, 0};
>
> -struct isa_ext_data {
> -    const char *name;
> -    int min_version;
> -    int ext_enable_offset;
> -};
> -
> -#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
> -    {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
> -
>  /*
>   * From vector_helper.c
>   * Note that vector data is stored in host-endian 64-bit chunks,
> @@ -61,6 +52,9 @@ struct isa_ext_data {
>  #define BYTE(x)   (x)
>  #endif
>
> +#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
> +    {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
> +
>  /*
>   * Here are the ordering rules of extension naming defined by RISC-V
>   * specification :
> @@ -81,7 +75,7 @@ struct isa_ext_data {
>   * Single letter extensions are checked in riscv_cpu_validate_misa_priv()
>   * instead.
>   */
> -static const struct isa_ext_data isa_edata_arr[] = {
> +const RISCVIsaExtData isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom),
>      ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
>      ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
> @@ -160,6 +154,8 @@ static const struct isa_ext_data isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, 
> ext_xtheadmempair),
>      ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync),
>      ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, 
> ext_XVentanaCondOps),
> +
> +    DEFINE_PROP_END_OF_LIST(),
>  };
>
>  bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
> @@ -178,14 +174,14 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t 
> ext_offset, bool en)
>
>  int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
>  {
> -    int i;
> +    const RISCVIsaExtData *edata;
>
> -    for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
> -        if (isa_edata_arr[i].ext_enable_offset != ext_offset) {
> +    for (edata = isa_edata_arr; edata && edata->name; edata++) {
> +        if (edata->ext_enable_offset != ext_offset) {
>              continue;
>          }
>
> -        return isa_edata_arr[i].min_version;
> +        return edata->min_version;
>      }
>
>      g_assert_not_reached();
> @@ -932,22 +928,21 @@ static void riscv_cpu_disas_set_info(CPUState *s, 
> disassemble_info *info)
>  void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
>  {
>      CPURISCVState *env = &cpu->env;
> -    int i;
> +    const RISCVIsaExtData *edata;
>
>      /* Force disable extensions if priv spec version does not match */
> -    for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
> -        if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) &&
> -            (env->priv_ver < isa_edata_arr[i].min_version)) {
> -            isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset,
> -                                   false);
> +    for (edata = isa_edata_arr; edata && edata->name; edata++) {
> +        if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) &&
> +            (env->priv_ver < edata->min_version)) {
> +            isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
>  #ifndef CONFIG_USER_ONLY
>              warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
>                          " because privilege spec version does not match",
> -                        isa_edata_arr[i].name, env->mhartid);
> +                        edata->name, env->mhartid);
>  #else
>              warn_report("disabling %s extension because "
>                          "privilege spec version does not match",
> -                        isa_edata_arr[i].name);
> +                        edata->name);
>  #endif
>          }
>      }
> @@ -1619,13 +1614,13 @@ static void riscv_cpu_class_init(ObjectClass *c, void 
> *data)
>  static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
>                                   int max_str_len)
>  {
> +    const RISCVIsaExtData *edata;
>      char *old = *isa_str;
>      char *new = *isa_str;
> -    int i;
>
> -    for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
> -        if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) {
> -            new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
> +    for (edata = isa_edata_arr; edata && edata->name; edata++) {
> +        if (isa_ext_is_enabled(cpu, edata->ext_enable_offset)) {
> +            new = g_strconcat(old, "_", edata->name, NULL);
>              g_free(old);
>              old = new;
>          }
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index aba8192c74..3dfcd0732f 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -726,6 +726,13 @@ extern const RISCVCPUMultiExtConfig 
> riscv_cpu_vendor_exts[];
>  extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
>  extern Property riscv_cpu_options[];
>
> +typedef struct isa_ext_data {
> +    const char *name;
> +    int min_version;
> +    int ext_enable_offset;
> +} RISCVIsaExtData;
> +extern const RISCVIsaExtData isa_edata_arr[];
> +
>  void riscv_add_satp_mode_properties(Object *obj);
>
>  /* CSR function table */
> --
> 2.41.0
>
>