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[PATCH v4 17/19] target/riscv/tcg: move riscv_cpu_add_misa_properties()
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From: |
Daniel Henrique Barboza |
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Subject: |
[PATCH v4 17/19] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c |
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Date: |
Mon, 25 Sep 2023 14:57:07 -0300 |
All code related to MISA TCG properties is also moved.
At this point, all TCG properties handling is done in tcg-cpu.c, all KVM
properties handling is done in kvm-cpu.c.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 90 --------------------------------------
target/riscv/cpu.h | 1 -
target/riscv/tcg/tcg-cpu.c | 90 ++++++++++++++++++++++++++++++++++++++
3 files changed, 90 insertions(+), 91 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4875feded7..46263e55d5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1211,47 +1211,6 @@ static void riscv_cpu_init(Object *obj)
#endif /* CONFIG_USER_ONLY */
}
-typedef struct RISCVCPUMisaExtConfig {
- target_ulong misa_bit;
- bool enabled;
-} RISCVCPUMisaExtConfig;
-
-static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
- target_ulong misa_bit = misa_ext_cfg->misa_bit;
- RISCVCPU *cpu = RISCV_CPU(obj);
- CPURISCVState *env = &cpu->env;
- bool value;
-
- if (!visit_type_bool(v, name, &value, errp)) {
- return;
- }
-
- if (value) {
- env->misa_ext |= misa_bit;
- env->misa_ext_mask |= misa_bit;
- } else {
- env->misa_ext &= ~misa_bit;
- env->misa_ext_mask &= ~misa_bit;
- }
-}
-
-static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
- target_ulong misa_bit = misa_ext_cfg->misa_bit;
- RISCVCPU *cpu = RISCV_CPU(obj);
- CPURISCVState *env = &cpu->env;
- bool value;
-
- value = env->misa_ext & misa_bit;
-
- visit_type_bool(v, name, &value, errp);
-}
-
typedef struct misa_ext_info {
const char *name;
const char *description;
@@ -1312,55 +1271,6 @@ const char *riscv_get_misa_ext_description(uint32_t bit)
return val;
}
-#define MISA_CFG(_bit, _enabled) \
- {.misa_bit = _bit, .enabled = _enabled}
-
-static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
- MISA_CFG(RVA, true),
- MISA_CFG(RVC, true),
- MISA_CFG(RVD, true),
- MISA_CFG(RVF, true),
- MISA_CFG(RVI, true),
- MISA_CFG(RVE, false),
- MISA_CFG(RVM, true),
- MISA_CFG(RVS, true),
- MISA_CFG(RVU, true),
- MISA_CFG(RVH, true),
- MISA_CFG(RVJ, false),
- MISA_CFG(RVV, false),
- MISA_CFG(RVG, false),
-};
-
-/*
- * We do not support user choice tracking for MISA
- * extensions yet because, so far, we do not silently
- * change MISA bits during realize() (RVG enables MISA
- * bits but the user is warned about it).
- */
-void riscv_cpu_add_misa_properties(Object *cpu_obj)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
- const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
- int bit = misa_cfg->misa_bit;
- const char *name = riscv_get_misa_ext_name(bit);
- const char *desc = riscv_get_misa_ext_description(bit);
-
- /* Check if KVM already created the property */
- if (object_property_find(cpu_obj, name)) {
- continue;
- }
-
- object_property_add(cpu_obj, name, "bool",
- cpu_get_misa_ext_cfg,
- cpu_set_misa_ext_cfg,
- NULL, (void *)misa_cfg);
- object_property_set_description(cpu_obj, name, desc);
- object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
- }
-}
-
#define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
{.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
.enabled = _defval}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 01cbcbe119..aba8192c74 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -726,7 +726,6 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
extern Property riscv_cpu_options[];
-void riscv_cpu_add_misa_properties(Object *cpu_obj);
void riscv_add_satp_mode_properties(Object *obj);
/* CSR function table */
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index ac3cf4c035..8065572703 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -580,6 +580,96 @@ static bool tcg_cpu_realizefn(CPUState *cs, Error **errp)
return true;
}
+typedef struct RISCVCPUMisaExtConfig {
+ target_ulong misa_bit;
+ bool enabled;
+} RISCVCPUMisaExtConfig;
+
+static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
+ target_ulong misa_bit = misa_ext_cfg->misa_bit;
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ CPURISCVState *env = &cpu->env;
+ bool value;
+
+ if (!visit_type_bool(v, name, &value, errp)) {
+ return;
+ }
+
+ if (value) {
+ env->misa_ext |= misa_bit;
+ env->misa_ext_mask |= misa_bit;
+ } else {
+ env->misa_ext &= ~misa_bit;
+ env->misa_ext_mask &= ~misa_bit;
+ }
+}
+
+static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
+ target_ulong misa_bit = misa_ext_cfg->misa_bit;
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ CPURISCVState *env = &cpu->env;
+ bool value;
+
+ value = env->misa_ext & misa_bit;
+
+ visit_type_bool(v, name, &value, errp);
+}
+
+#define MISA_CFG(_bit, _enabled) \
+ {.misa_bit = _bit, .enabled = _enabled}
+
+static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
+ MISA_CFG(RVA, true),
+ MISA_CFG(RVC, true),
+ MISA_CFG(RVD, true),
+ MISA_CFG(RVF, true),
+ MISA_CFG(RVI, true),
+ MISA_CFG(RVE, false),
+ MISA_CFG(RVM, true),
+ MISA_CFG(RVS, true),
+ MISA_CFG(RVU, true),
+ MISA_CFG(RVH, true),
+ MISA_CFG(RVJ, false),
+ MISA_CFG(RVV, false),
+ MISA_CFG(RVG, false),
+};
+
+/*
+ * We do not support user choice tracking for MISA
+ * extensions yet because, so far, we do not silently
+ * change MISA bits during realize() (RVG enables MISA
+ * bits but the user is warned about it).
+ */
+static void riscv_cpu_add_misa_properties(Object *cpu_obj)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
+ const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
+ int bit = misa_cfg->misa_bit;
+ const char *name = riscv_get_misa_ext_name(bit);
+ const char *desc = riscv_get_misa_ext_description(bit);
+
+ /* Check if KVM already created the property */
+ if (object_property_find(cpu_obj, name)) {
+ continue;
+ }
+
+ object_property_add(cpu_obj, name, "bool",
+ cpu_get_misa_ext_cfg,
+ cpu_set_misa_ext_cfg,
+ NULL, (void *)misa_cfg);
+ object_property_set_description(cpu_obj, name, desc);
+ object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
+ }
+}
+
static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
--
2.41.0
- [PATCH v4 07/19] target/riscv/cpu.c: mark extensions arrays as 'const', (continued)
- [PATCH v4 07/19] target/riscv/cpu.c: mark extensions arrays as 'const', Daniel Henrique Barboza, 2023/09/25
- [PATCH v4 08/19] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c, Daniel Henrique Barboza, 2023/09/25
- [PATCH v4 10/19] target/riscv: remove kvm-stub.c, Daniel Henrique Barboza, 2023/09/25
- [PATCH v4 11/19] target/riscv: introduce KVM AccelCPUClass, Daniel Henrique Barboza, 2023/09/25
- [PATCH v4 09/19] target/riscv: make riscv_add_satp_mode_properties() public, Daniel Henrique Barboza, 2023/09/25
- [PATCH v4 12/19] target/riscv: move KVM only files to kvm subdir, Daniel Henrique Barboza, 2023/09/25
- [PATCH v4 13/19] target/riscv/kvm: do not use riscv_cpu_add_misa_properties(), Daniel Henrique Barboza, 2023/09/25
- [PATCH v4 14/19] target/riscv/cpu.c: export set_misa(), Daniel Henrique Barboza, 2023/09/25
- [PATCH v4 15/19] target/riscv/tcg: introduce tcg_cpu_instance_init(), Daniel Henrique Barboza, 2023/09/25
- [PATCH v4 16/19] target/riscv/cpu.c: make misa_ext_cfgs[] 'const', Daniel Henrique Barboza, 2023/09/25
- [PATCH v4 17/19] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c,
Daniel Henrique Barboza <=
- [PATCH v4 18/19] target/riscv/cpu.c: export isa_edata_arr[], Daniel Henrique Barboza, 2023/09/25
- [PATCH v4 19/19] target/riscv/cpu: move priv spec functions to tcg-cpu.c, Daniel Henrique Barboza, 2023/09/25
- Re: [PATCH v4 00/19] riscv: split TCG/KVM accelerators from cpu.c, Alistair Francis, 2023/09/25