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[PATCH 0/3] Support discontinuous PMU counters
From: |
Rob Bradford |
Subject: |
[PATCH 0/3] Support discontinuous PMU counters |
Date: |
Tue, 3 Oct 2023 13:49:34 +0100 |
Currently the available PMU counters start at HPM3 and run through to
the number specified by the "pmu-num" property. There is no
requirement in the specification that the available counters be
continously numbered. This series add suppport for specifying a
discountinuous range of counters though a "pmu-mask" property.
Rob Bradford (3):
target/riscv: Propagate error from PMU setup
target/riscv: Support discontinuous PMU counters
target/riscv: Don't assume PMU counters are continuous
target/riscv/cpu.c | 9 ++++++++-
target/riscv/cpu_cfg.h | 1 +
target/riscv/csr.c | 5 +++--
target/riscv/pmu.c | 32 +++++++++++++++++++++-----------
target/riscv/pmu.h | 3 ++-
5 files changed, 35 insertions(+), 15 deletions(-)
--
2.41.0
- [PATCH 0/3] Support discontinuous PMU counters,
Rob Bradford <=
- [PATCH 1/3] target/riscv: Propagate error from PMU setup, Rob Bradford, 2023/10/03
- [PATCH 2/3] target/riscv: Support discontinuous PMU counters, Rob Bradford, 2023/10/03
- Re: [PATCH 2/3] target/riscv: Support discontinuous PMU counters, Atish Kumar Patra, 2023/10/03
- Re: [PATCH 2/3] target/riscv: Support discontinuous PMU counters, Rob Bradford, 2023/10/04
- Re: [PATCH 2/3] target/riscv: Support discontinuous PMU counters, Alistair Francis, 2023/10/08
- Re: [PATCH 2/3] target/riscv: Support discontinuous PMU counters, Atish Kumar Patra, 2023/10/09
- Re: [PATCH 2/3] target/riscv: Support discontinuous PMU counters, Alistair Francis, 2023/10/10
- Re: [PATCH 2/3] target/riscv: Support discontinuous PMU counters, Rob Bradford, 2023/10/11
- Re: [PATCH 2/3] target/riscv: Support discontinuous PMU counters, Alistair Francis, 2023/10/16