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[PATCH v2 09/10] target/riscv/tcg: handle MISA bits on profile commit
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v2 09/10] target/riscv/tcg: handle MISA bits on profile commit |
Date: |
Fri, 6 Oct 2023 10:21:33 -0300 |
The profile support is handling multi-letter extensions only. Let's add
support for MISA bits as well.
We'll go through every known MISA bit. If the user set the bit, doesn't
matter if to 'true' or 'false', ignore it. If the profile doesn't
declare the bit as mandatory, ignore it. Otherwise, set or clear the bit
in env->misa_ext and env->misa_ext_mask depending on whether the profile
was set to 'true' or 'false'.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/tcg/tcg-cpu.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index b1e778913c..d7540274f4 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -42,6 +42,12 @@ static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
GUINT_TO_POINTER(ext_offset));
}
+static bool cpu_misa_ext_is_user_set(uint32_t misa_bit)
+{
+ return g_hash_table_contains(misa_ext_user_opts,
+ GUINT_TO_POINTER(misa_bit));
+}
+
static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit,
bool enabled)
{
@@ -283,6 +289,20 @@ static void riscv_cpu_commit_profile(RISCVCPU *cpu,
RISCVCPUProfile *profile)
{
int i;
+ for (i = 0; misa_bits[i] != 0; i++) {
+ uint32_t bit = misa_bits[i];
+
+ if (cpu_misa_ext_is_user_set(bit) || !(profile->misa_ext & bit)) {
+ continue;
+ }
+
+ g_hash_table_insert(misa_ext_user_opts,
+ GUINT_TO_POINTER(bit),
+ (gpointer)profile->enabled);
+
+ riscv_cpu_write_misa_bit(cpu, bit, profile->enabled);
+ }
+
for (i = 0;; i++) {
int ext_offset = profile->ext_offsets[i];
--
2.41.0
- [PATCH v2 03/10] target/riscv: add rva22u64 profile definition, (continued)
- [PATCH v2 03/10] target/riscv: add rva22u64 profile definition, Daniel Henrique Barboza, 2023/10/06
- [PATCH v2 05/10] target/riscv/tcg: add user flag for profile support, Daniel Henrique Barboza, 2023/10/06
- [PATCH v2 04/10] target/riscv/kvm: add 'rva22u64' flag as unavailable, Daniel Henrique Barboza, 2023/10/06
- [PATCH v2 07/10] target/riscv/tcg: add MISA user options hash, Daniel Henrique Barboza, 2023/10/06
- [PATCH v2 06/10] target/riscv/tcg: commit profiles during realize(), Daniel Henrique Barboza, 2023/10/06
- [PATCH v2 08/10] target/riscv/tcg: add riscv_cpu_write_misa_bit(), Daniel Henrique Barboza, 2023/10/06
- [PATCH v2 09/10] target/riscv/tcg: handle MISA bits on profile commit,
Daniel Henrique Barboza <=
- [PATCH v2 10/10] target/riscv/tcg: add hash table insert helpers, Daniel Henrique Barboza, 2023/10/06
- Re: [PATCH v2 00/10] riscv: RVA22U64 profile support, Alistair Francis, 2023/10/10
- Re: [PATCH v2 00/10] riscv: RVA22U64 profile support, Daniel Henrique Barboza, 2023/10/12
- Re: [PATCH v2 00/10] riscv: RVA22U64 profile support, Alistair Francis, 2023/10/15
- Re: [PATCH v2 00/10] riscv: RVA22U64 profile support, Andrew Jones, 2023/10/16
- Re: [PATCH v2 00/10] riscv: RVA22U64 profile support, Alistair Francis, 2023/10/16
- Re: [PATCH v2 00/10] riscv: RVA22U64 profile support, Andrew Jones, 2023/10/17
- Re: [PATCH v2 00/10] riscv: RVA22U64 profile support, Daniel Henrique Barboza, 2023/10/18