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[PATCH 4/4] target/riscv: rename ext_icboz to ext_zicboz
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH 4/4] target/riscv: rename ext_icboz to ext_zicboz |
Date: |
Thu, 12 Oct 2023 13:46:04 -0300 |
Add a leading 'z' to improve grepping. When one wants to search for uses
of zicboz they're more likely to do 'grep -i zicboz' than 'grep -i
icboz'.
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
hw/riscv/virt.c | 2 +-
target/riscv/cpu.c | 6 +++---
target/riscv/cpu_cfg.h | 2 +-
target/riscv/insn_trans/trans_rvzicbo.c.inc | 8 ++++----
target/riscv/kvm/kvm-cpu.c | 6 +++---
5 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 54e0fe8ecc..1732c42915 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -268,7 +268,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int
socket,
cpu_ptr->cfg.cbom_blocksize);
}
- if (cpu_ptr->cfg.ext_icboz) {
+ if (cpu_ptr->cfg.ext_zicboz) {
qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size",
cpu_ptr->cfg.cboz_blocksize);
}
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c9020653cd..46a256fccc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -77,7 +77,7 @@ const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD,
RVV,
*/
const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_zicbom),
- ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
+ ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_zicboz),
ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr),
ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_zifencei),
@@ -500,7 +500,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
cpu->cfg.ext_zicbom = true;
cpu->cfg.cbom_blocksize = 64;
cpu->cfg.cboz_blocksize = 64;
- cpu->cfg.ext_icboz = true;
+ cpu->cfg.ext_zicboz = true;
cpu->cfg.ext_smaia = true;
cpu->cfg.ext_ssaia = true;
cpu->cfg.ext_sscofpmf = true;
@@ -1285,7 +1285,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false),
MULTI_EXT_CFG_BOOL("zicbom", ext_zicbom, true),
- MULTI_EXT_CFG_BOOL("zicboz", ext_icboz, true),
+ MULTI_EXT_CFG_BOOL("zicboz", ext_zicboz, true),
MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false),
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index e6bef0070f..208cac1c7c 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -64,7 +64,7 @@ struct RISCVCPUConfig {
bool ext_zifencei;
bool ext_zicsr;
bool ext_zicbom;
- bool ext_icboz;
+ bool ext_zicboz;
bool ext_zicond;
bool ext_zihintntl;
bool ext_zihintpause;
diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc
b/target/riscv/insn_trans/trans_rvzicbo.c.inc
index e6ed548376..d5d7095903 100644
--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
@@ -22,10 +22,10 @@
} \
} while (0)
-#define REQUIRE_ZICBOZ(ctx) do { \
- if (!ctx->cfg_ptr->ext_icboz) { \
- return false; \
- } \
+#define REQUIRE_ZICBOZ(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zicboz) { \
+ return false; \
+ } \
} while (0)
static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index ad48c9bf30..5695f2face 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -214,7 +214,7 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu,
CPUState *cs)
static KVMCPUConfig kvm_multi_ext_cfgs[] = {
KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM),
- KVM_EXT_CFG("zicboz", ext_icboz, KVM_RISCV_ISA_EXT_ZICBOZ),
+ KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ),
KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE),
KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB),
KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA),
@@ -808,7 +808,7 @@ static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu,
kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize);
}
- if (cpu->cfg.ext_icboz) {
+ if (cpu->cfg.ext_zicboz) {
kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize);
}
}
@@ -901,7 +901,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu,
KVMScratchCPU *kvmcpu)
kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize);
}
- if (cpu->cfg.ext_icboz) {
+ if (cpu->cfg.ext_zicboz) {
kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize);
}
}
--
2.41.0
- [PATCH 0/4] target/riscv: rename ext_i* to ext_zi*, Daniel Henrique Barboza, 2023/10/12
- [PATCH 1/4] target/riscv: rename ext_ifencei to ext_zifencei, Daniel Henrique Barboza, 2023/10/12
- [PATCH 2/4] target/riscv: rename ext_icsr to ext_zicsr, Daniel Henrique Barboza, 2023/10/12
- [PATCH 3/4] target/riscv: rename ext_icbom to ext_zicbom, Daniel Henrique Barboza, 2023/10/12
- [PATCH 4/4] target/riscv: rename ext_icboz to ext_zicboz,
Daniel Henrique Barboza <=
- Re: [PATCH 0/4] target/riscv: rename ext_i* to ext_zi*, Andrew Jones, 2023/10/13
- Re: [PATCH 0/4] target/riscv: rename ext_i* to ext_zi*, Alistair Francis, 2023/10/16