Re: [PATCH v2 2/6] qapi,risc-v: add query-cpu-model-expansion

[Alistair Francis]

On Wed, Sep 27, 2023 at 4:41 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> This API is used to inspect the characteristics of a given CPU model. It
> also allows users to validate a CPU model with a certain configuration,
> e.g. if "-cpu X,a=true,b=false" is a valid setup for a given QEMU
> binary. We'll start implementing the first part. The second requires
> more changes in RISC-V CPU boot flow.
>
> The implementation is inspired by the existing ARM
> query-cpu-model-expansion impl in target/arm/arm-qmp-cmds.c. We'll
> create a RISCVCPU object with the required model, fetch its existing
> properties, add a couple of relevant boolean options (pmp and mmu) and
> display it to users.
>
> Here's an usage example:
>
> ./build/qemu-system-riscv64 -S -M virt -display none \
>   -qmp  tcp:localhost:1234,server,wait=off
>
> ./scripts/qmp/qmp-shell localhost:1234
> Welcome to the QMP low-level shell!
> Connected to QEMU 8.1.50
>
> (QEMU)  query-cpu-model-expansion type=full model={"name":"rv64"}
> {"return": {"model": {"name": "rv64", "props": {"zicond": false, "x-zvfh": 
> false, "mmu": true, "x-zvfbfwma": false, "x-zvfbfmin": false, "xtheadbs": 
> false, "xtheadbb": false, "xtheadba": false, "xtheadmemidx": false, 
> "smstateen": false, "zfinx": false, "Zve64f": false, "Zve32f": false, 
> "x-zvfhmin": false, "xventanacondops": false, "xtheadcondmov": false, 
> "svpbmt": false, "zbs": true, "zbc": true, "zbb": true, "zba": true, 
> "zicboz": true, "xtheadmac": false, "Zfh": false, "Zfa": true, "zbkx": false, 
> "zbkc": false, "zbkb": false, "Zve64d": false, "x-zfbfmin": false, "zk": 
> false, "x-epmp": false, "xtheadmempair": false, "zkt": false, "zks": false, 
> "zkr": false, "zkn": false, "Zfhmin": false, "zksh": false, "zknh": false, 
> "zkne": false, "zknd": false, "zhinx": false, "Zicsr": true, "sscofpmf": 
> false, "Zihintntl": true, "sstc": true, "xtheadcmo": false, "x-zvbb": false, 
> "zksed": false, "x-zvkned": false, "xtheadsync": false, "x-zvkg": false, 
> "zhinxmin": false, "svadu": true, "xtheadfmv": false, "x-zvksed": false, 
> "svnapot": false, "pmp": true, "x-zvknhb": false, "x-zvknha": false, 
> "xtheadfmemidx": false, "x-zvksh": false, "zdinx": false, "zicbom": true, 
> "Zihintpause": true, "svinval": false, "zcf": false, "zce": false, "zcd": 
> false, "zcb": false, "zca": false, "x-ssaia": false, "x-smaia": false, 
> "zmmul": false, "x-zvbc": false, "Zifencei": true, "zcmt": false, "zcmp": 
> false, "Zawrs": true}}}}
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  qapi/machine-target.json      |  6 ++-
>  target/riscv/riscv-qmp-cmds.c | 75 +++++++++++++++++++++++++++++++++++
>  2 files changed, 79 insertions(+), 2 deletions(-)
>
> diff --git a/qapi/machine-target.json b/qapi/machine-target.json
> index f0a6b72414..e5630e73aa 100644
> --- a/qapi/machine-target.json
> +++ b/qapi/machine-target.json
> @@ -228,7 +228,8 @@
>    'data': { 'model': 'CpuModelInfo' },
>    'if': { 'any': [ 'TARGET_S390X',
>                     'TARGET_I386',
> -                   'TARGET_ARM' ] } }
> +                   'TARGET_ARM',
> +                   'TARGET_RISCV' ] } }
>
>  ##
>  # @query-cpu-model-expansion:
> @@ -273,7 +274,8 @@
>    'returns': 'CpuModelExpansionInfo',
>    'if': { 'any': [ 'TARGET_S390X',
>                     'TARGET_I386',
> -                   'TARGET_ARM' ] } }
> +                   'TARGET_ARM',
> +                   'TARGET_RISCV' ] } }
>
>  ##
>  # @CpuDefinitionInfo:
> diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c
> index 5ecff1afb3..2170562e3a 100644
> --- a/target/riscv/riscv-qmp-cmds.c
> +++ b/target/riscv/riscv-qmp-cmds.c
> @@ -24,8 +24,12 @@
>
>  #include "qemu/osdep.h"
>
> +#include "qapi/error.h"
>  #include "qapi/qapi-commands-machine-target.h"
> +#include "qapi/qmp/qdict.h"
> +#include "qom/qom-qobject.h"
>  #include "cpu-qom.h"
> +#include "cpu.h"
>
>  static void riscv_cpu_add_definition(gpointer data, gpointer user_data)
>  {
> @@ -55,3 +59,74 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error 
> **errp)
>
>      return cpu_list;
>  }
> +
> +static void riscv_obj_add_qdict_prop(Object *obj, QDict *qdict_out,
> +                                     const char *name)
> +{
> +    ObjectProperty *prop = object_property_find(obj, name);
> +
> +    if (prop) {
> +        QObject *value;
> +
> +        assert(prop->get);
> +        value = object_property_get_qobject(obj, name, &error_abort);
> +
> +        qdict_put_obj(qdict_out, name, value);
> +    }
> +}
> +
> +static void riscv_obj_add_multiext_props(Object *obj, QDict *qdict_out,
> +                                         const RISCVCPUMultiExtConfig *arr)
> +{
> +    for (int i = 0; arr[i].name != NULL; i++) {
> +        riscv_obj_add_qdict_prop(obj, qdict_out, arr[i].name);
> +    }
> +}
> +
> +CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType 
> type,
> +                                                     CpuModelInfo *model,
> +                                                     Error **errp)
> +{
> +    CpuModelExpansionInfo *expansion_info;
> +    QDict *qdict_out;
> +    ObjectClass *oc;
> +    Object *obj;
> +
> +    if (type != CPU_MODEL_EXPANSION_TYPE_FULL) {
> +        error_setg(errp, "The requested expansion type is not supported");
> +        return NULL;
> +    }
> +
> +    oc = cpu_class_by_name(TYPE_RISCV_CPU, model->name);
> +    if (!oc) {
> +        error_setg(errp, "The CPU type '%s' is not a known RISC-V CPU type",
> +                   model->name);
> +        return NULL;
> +    }
> +
> +    obj = object_new(object_class_get_name(oc));
> +
> +    expansion_info = g_new0(CpuModelExpansionInfo, 1);
> +    expansion_info->model = g_malloc0(sizeof(*expansion_info->model));
> +    expansion_info->model->name = g_strdup(model->name);
> +
> +    qdict_out = qdict_new();
> +
> +    riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_extensions);
> +    riscv_obj_add_multiext_props(obj, qdict_out, 
> riscv_cpu_experimental_exts);
> +    riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_vendor_exts);
> +
> +    /* Add our CPU boolean options too */
> +    riscv_obj_add_qdict_prop(obj, qdict_out, "mmu");
> +    riscv_obj_add_qdict_prop(obj, qdict_out, "pmp");
> +
> +    if (!qdict_size(qdict_out)) {
> +        qobject_unref(qdict_out);
> +    } else {
> +        expansion_info->model->props = QOBJECT(qdict_out);
> +    }
> +
> +    object_unref(obj);
> +
> +    return expansion_info;
> +}
> --
> 2.41.0
>
>