Re: [PATCH v5 0/6] target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support

[Alistair Francis]

On Mon, Oct 16, 2023 at 9:19 PM Rajnesh Kanwal <rkanwal@rivosinc.com> wrote:
>
> This series adds M and HS-mode virtual interrupt and IRQ filtering support.
> This allows inserting virtual interrupts from M/HS-mode into S/VS-mode
> using mvien/hvien and mvip/hvip csrs. IRQ filtering is a use case of
> this change, i-e M-mode can stop delegating an interrupt to S-mode and
> instead enable it in MIE and receive those interrupts in M-mode and then
> selectively inject the interrupt using mvien and mvip.
>
> Also, the spec doesn't mandate the interrupt to be actually supported
> in hardware. Which allows M/HS-mode to assert virtual interrupts to
> S/VS-mode that have no connection to any real interrupt events.
>
> This is defined as part of the AIA specification [0], "5.3 Interrupt
> filtering and virtual interrupts for supervisor level" and "6.3.2 Virtual
> interrupts for VS level".
>
> Most of the testing is done by hacking around OpenSBI and linux host.
> The changes for those can be found at [1] and [2].
>
> It's my first touch on RISC-V qemu IRQ subsystem. Any feedback would
> be much appreciated.
>
> The change can also be found on github [3].
>
> TODO: This change doesn't support delegating virtual interrupts injected
> by M-mode to VS-mode by the Hypervisor. This is true for bits 13:63 only.

Thanks!

Applied to riscv-to-apply.next

Alistair

>
> Thanks
> Rajnesh
>
> [0]: 
> https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf
> [1]: https://github.com/rajnesh-kanwal/opensbi/tree/dev/rkanwal/irq_filter
> [2]: 
> https://github.com/rajnesh-kanwal/linux/commits/dev/rkanwal/aia_irq_filter
> [3]: https://github.com/rajnesh-kanwal/qemu/tree/dev/rkanwal/riscv_irq_filter
>
> v5:
>  * Rebased the patches onto alister/riscv-to-apply.next again. Updated
>    version_id and minimum_version_id in vmstate_riscv_cpu and
>    vmstate_hyper. Also updated AIA spec links.
>
> v4:
>  * Rebased the patches onto alister/riscv-to-apply.next. There were
>    some rebasing conflicts due to code restructuring.
>
> v3:
>  * Rebased the patches and added reviewed-by tags.
>
> v2:
>  * Move RISCV_EXCP_SEMIHOST to switch case and remove special handling.
>  * Fix linux-user build.
>
> Rajnesh Kanwal (6):
>   target/riscv: Without H-mode mask all HS mode inturrupts in mie.
>   target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.
>   target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled
>   target/riscv: Split interrupt logic from riscv_cpu_update_mip.
>   target/riscv: Add M-mode virtual interrupt and IRQ filtering support.
>   target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.
>
>  target/riscv/cpu.c         |   4 +-
>  target/riscv/cpu.h         |  23 ++
>  target/riscv/cpu_bits.h    |   6 +
>  target/riscv/cpu_helper.c  |  99 ++++++--
>  target/riscv/csr.c         | 477 +++++++++++++++++++++++++++++++++----
>  target/riscv/machine.c     |  14 +-
>  target/riscv/tcg/tcg-cpu.c |   7 +-
>  7 files changed, 551 insertions(+), 79 deletions(-)
>
> --
> 2.34.1
>
>