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[PATCH v2 5/6] target/riscv/tcg: add ext_zihpm disable support
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v2 5/6] target/riscv/tcg: add ext_zihpm disable support |
Date: |
Tue, 17 Oct 2023 19:12:25 -0300 |
Disabling ext_zihpm does nothing at this moment. Add support to disable
the hpmcounter3-hpmcounter31 counters if the user disables zihpm.
There is already code in place in target/riscv/csr.c in all predicates
for these counters (ctr() and mctr()) that disables them if
cpu->cfg.pmu_num is zero. Thus, setting cpu->cfg.pmu_num to zero if
'zihpm=false' is enough to disable the extension.
Set cpu->pmu_avail_ctrs mask to zero as well since this is also checked
to verify if the counters exist.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/tcg/tcg-cpu.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index a01b876621..7a4400e2ba 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -549,6 +549,19 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
Error **errp)
cpu->cfg.ext_zicntr = false;
}
+ if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) {
+ if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zihpm))) {
+ error_setg(errp, "zihpm requires zicsr");
+ return;
+ }
+ cpu->cfg.ext_zihpm = false;
+ }
+
+ if (!cpu->cfg.ext_zihpm) {
+ cpu->cfg.pmu_num = 0;
+ cpu->pmu_avail_ctrs = 0;
+ }
+
/*
* Disable isa extensions based on priv spec after we
* validated and set everything we need.
--
2.41.0
- [PATCH v2 0/6] riscv: zicntr/zihpm flags and disable support, Daniel Henrique Barboza, 2023/10/17
- [PATCH v2 2/6] target/riscv/tcg: add ext_zicntr disable support, Daniel Henrique Barboza, 2023/10/17
- [PATCH v2 1/6] target/riscv/cpu.c: add zicntr extension flag, Daniel Henrique Barboza, 2023/10/17
- [PATCH v2 4/6] target/riscv/cpu.c: add zihpm extension flag, Daniel Henrique Barboza, 2023/10/17
- [PATCH v2 5/6] target/riscv/tcg: add ext_zihpm disable support,
Daniel Henrique Barboza <=
- [PATCH v2 3/6] target/riscv/kvm: add zicntr reg, Daniel Henrique Barboza, 2023/10/17
- [PATCH v2 6/6] target/riscv/kvm: add zihpm reg, Daniel Henrique Barboza, 2023/10/17