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Re: [PATCH v4 3/6] target/riscv: Use existing PMU counter mask in FDT ge
From: |
Atish Kumar Patra |
Subject: |
Re: [PATCH v4 3/6] target/riscv: Use existing PMU counter mask in FDT generation |
Date: |
Mon, 23 Oct 2023 17:06:21 -0700 |
On Wed, Oct 18, 2023 at 8:44 AM Rob Bradford <rbradford@rivosinc.com> wrote:
>
> During the FDT generation use the existing mask containing the enabled
> counters rather then generating a new one. Using the existing mask will
> support the use of discontinuous counters.
>
> Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/virt.c | 2 +-
> target/riscv/pmu.c | 6 +-----
> target/riscv/pmu.h | 2 +-
> 3 files changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 9de578c756..241681f98d 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -722,7 +722,7 @@ static void create_fdt_pmu(RISCVVirtState *s)
> pmu_name = g_strdup_printf("/pmu");
> qemu_fdt_add_subnode(ms->fdt, pmu_name);
> qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu");
> - riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name);
> + riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name);
>
> g_free(pmu_name);
> }
> diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
> index 13801ccb78..7ddf4977b1 100644
> --- a/target/riscv/pmu.c
> +++ b/target/riscv/pmu.c
> @@ -34,13 +34,9 @@
> * to provide the correct value as well. Heterogeneous PMU per hart is not
> * supported yet. Thus, number of counters are same across all harts.
> */
> -void riscv_pmu_generate_fdt_node(void *fdt, int num_ctrs, char *pmu_name)
> +void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name)
> {
> uint32_t fdt_event_ctr_map[15] = {};
> - uint32_t cmask;
> -
> - /* All the programmable counters can map to any event */
> - cmask = MAKE_32BIT_MASK(3, num_ctrs);
>
> /*
> * The event encoding is specified in the SBI specification
> diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h
> index 88e0713296..505fc850d3 100644
> --- a/target/riscv/pmu.h
> +++ b/target/riscv/pmu.h
> @@ -28,6 +28,6 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp);
> int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
> uint32_t ctr_idx);
> int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx);
> -void riscv_pmu_generate_fdt_node(void *fdt, int num_counters, char
> *pmu_name);
> +void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name);
> int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value,
> uint32_t ctr_idx);
> --
> 2.41.0
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
- [PATCH v4 0/6] Support discontinuous PMU counters, Rob Bradford, 2023/10/18
- [PATCH v4 1/6] target/riscv: Propagate error from PMU setup, Rob Bradford, 2023/10/18
- [PATCH v4 2/6] target/riscv: Don't assume PMU counters are continuous, Rob Bradford, 2023/10/18
- [PATCH v4 3/6] target/riscv: Use existing PMU counter mask in FDT generation, Rob Bradford, 2023/10/18
- Re: [PATCH v4 3/6] target/riscv: Use existing PMU counter mask in FDT generation,
Atish Kumar Patra <=
- [PATCH v4 4/6] target/riscv: Add "pmu-mask" property to replace "pmu-num", Rob Bradford, 2023/10/18
- [PATCH v4 5/6] docs/about/deprecated: Document RISC-V "pmu-num" deprecation, Rob Bradford, 2023/10/18
- [PATCH v4 6/6] target/riscv: Use MAKE_64BIT_MASK instead of custom macro, Rob Bradford, 2023/10/18