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[PATCH v5 06/10] target/riscv/tcg: add riscv_cpu_write_misa_bit()
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v5 06/10] target/riscv/tcg: add riscv_cpu_write_misa_bit() |
Date: |
Wed, 25 Oct 2023 20:44:55 -0300 |
We have two instances of the setting/clearing a MISA bit from
env->misa_ext and env->misa_ext_mask pattern. And the next patch will
end up adding one more.
Create a helper to avoid code repetition.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/tcg/tcg-cpu.c | 44 ++++++++++++++++++++------------------
1 file changed, 23 insertions(+), 21 deletions(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 9a0d85d6e6..5d96ccb45c 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -42,6 +42,20 @@ static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
GUINT_TO_POINTER(ext_offset));
}
+static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit,
+ bool enabled)
+{
+ CPURISCVState *env = &cpu->env;
+
+ if (enabled) {
+ env->misa_ext |= bit;
+ env->misa_ext_mask |= bit;
+ } else {
+ env->misa_ext &= ~bit;
+ env->misa_ext_mask &= ~bit;
+ }
+}
+
static void riscv_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
@@ -717,20 +731,14 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v,
const char *name,
return;
}
- if (value) {
- if (!generic_cpu) {
- g_autofree char *cpuname = riscv_cpu_get_name(cpu);
- error_setg(errp, "'%s' CPU does not allow enabling extensions",
- cpuname);
- return;
- }
-
- env->misa_ext |= misa_bit;
- env->misa_ext_mask |= misa_bit;
- } else {
- env->misa_ext &= ~misa_bit;
- env->misa_ext_mask &= ~misa_bit;
+ if (value && !generic_cpu) {
+ g_autofree char *cpuname = riscv_cpu_get_name(cpu);
+ error_setg(errp, "'%s' CPU does not allow enabling extensions",
+ cpuname);
+ return;
}
+
+ riscv_cpu_write_misa_bit(cpu, misa_bit, value);
}
static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
@@ -774,7 +782,6 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
*/
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
{
- CPURISCVState *env = &RISCV_CPU(cpu_obj)->env;
bool use_def_vals = riscv_cpu_is_generic(cpu_obj);
int i;
@@ -795,13 +802,8 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
NULL, (void *)misa_cfg);
object_property_set_description(cpu_obj, name, desc);
if (use_def_vals) {
- if (misa_cfg->enabled) {
- env->misa_ext |= bit;
- env->misa_ext_mask |= bit;
- } else {
- env->misa_ext &= ~bit;
- env->misa_ext_mask &= ~bit;
- }
+ riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit,
+ misa_cfg->enabled);
}
}
}
--
2.41.0
- [PATCH v5 00/10] RVA22U64 profile support, Daniel Henrique Barboza, 2023/10/25
- [PATCH v5 03/10] target/riscv/kvm: add 'rva22u64' flag as unavailable, Daniel Henrique Barboza, 2023/10/25
- [PATCH v5 02/10] target/riscv: add rva22u64 profile definition, Daniel Henrique Barboza, 2023/10/25
- [PATCH v5 04/10] target/riscv/tcg: add user flag for profile support, Daniel Henrique Barboza, 2023/10/25
- [PATCH v5 06/10] target/riscv/tcg: add riscv_cpu_write_misa_bit(),
Daniel Henrique Barboza <=
- [PATCH v5 05/10] target/riscv/tcg: add MISA user options hash, Daniel Henrique Barboza, 2023/10/25
- [PATCH v5 01/10] target/riscv/tcg: add 'zic64b' support, Daniel Henrique Barboza, 2023/10/25
- [PATCH v5 08/10] target/riscv/tcg: add hash table insert helpers, Daniel Henrique Barboza, 2023/10/25
- [PATCH v5 07/10] target/riscv/tcg: handle profile MISA bits, Daniel Henrique Barboza, 2023/10/25
- [PATCH v5 10/10] target/riscv/tcg: warn if profile exts are disabled, Daniel Henrique Barboza, 2023/10/25
- [PATCH v5 09/10] target/riscv/tcg: honor user choice for G MISA bits, Daniel Henrique Barboza, 2023/10/25