[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v6 09/12] target/riscv/tcg: handle profile MISA bits
|
From: |
Alistair Francis |
|
Subject: |
Re: [PATCH v6 09/12] target/riscv/tcg: handle profile MISA bits |
|
Date: |
Mon, 30 Oct 2023 13:48:50 +1000 |
On Sat, Oct 28, 2023 at 7:35 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> The profile support is handling multi-letter extensions only. Let's add
> support for MISA bits as well.
>
> We'll go through every known MISA bit. If the profile doesn't declare
> the bit as mandatory, ignore it. Otherwise, set the bit in env->misa_ext
> and env->misa_ext_mask.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/tcg/tcg-cpu.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 910360ce37..6ba27b824b 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -828,6 +828,19 @@ static void cpu_set_profile(Object *obj, Visitor *v,
> const char *name,
> return;
> }
>
> + for (i = 0; misa_bits[i] != 0; i++) {
> + uint32_t bit = misa_bits[i];
> +
> + if (!(profile->misa_ext & bit)) {
> + continue;
> + }
> +
> + g_hash_table_insert(misa_ext_user_opts,
> + GUINT_TO_POINTER(bit),
> + (gpointer)value);
> + riscv_cpu_write_misa_bit(cpu, bit, profile->enabled);
> + }
> +
> for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) {
> ext_offset = profile->ext_offsets[i];
>
> --
> 2.41.0
>
>
- [PATCH v6 03/12] riscv-qmp-cmds.c: expose named features in cpu_model_expansion, (continued)
- [PATCH v6 03/12] riscv-qmp-cmds.c: expose named features in cpu_model_expansion, Daniel Henrique Barboza, 2023/10/28
- [PATCH v6 04/12] target/riscv: add rva22u64 profile definition, Daniel Henrique Barboza, 2023/10/28
- [PATCH v6 05/12] target/riscv/kvm: add 'rva22u64' flag as unavailable, Daniel Henrique Barboza, 2023/10/28
- [PATCH v6 06/12] target/riscv/tcg: add user flag for profile support, Daniel Henrique Barboza, 2023/10/28
- [PATCH v6 07/12] target/riscv/tcg: add MISA user options hash, Daniel Henrique Barboza, 2023/10/28
- [PATCH v6 09/12] target/riscv/tcg: handle profile MISA bits, Daniel Henrique Barboza, 2023/10/28
- Re: [PATCH v6 09/12] target/riscv/tcg: handle profile MISA bits,
Alistair Francis <=
- [PATCH v6 08/12] target/riscv/tcg: add riscv_cpu_write_misa_bit(), Daniel Henrique Barboza, 2023/10/28
- [PATCH v6 10/12] target/riscv/tcg: add hash table insert helpers, Daniel Henrique Barboza, 2023/10/28
- [PATCH v6 11/12] target/riscv/tcg: honor user choice for G MISA bits, Daniel Henrique Barboza, 2023/10/28
- [PATCH v6 12/12] target/riscv/tcg: warn if profile exts are disabled, Daniel Henrique Barboza, 2023/10/28