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[PATCH v9 13/19] target/riscv/tcg: handle profile MISA bits
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v9 13/19] target/riscv/tcg: handle profile MISA bits |
Date: |
Thu, 2 Nov 2023 19:44:39 -0300 |
The profile support is handling multi-letter extensions only. Let's add
support for MISA bits as well.
We'll go through every known MISA bit. If the profile doesn't declare
the bit as mandatory, ignore it. Otherwise, set the bit in env->misa_ext
and env->misa_ext_mask.
Now that we're setting profile MISA bits, one can use the rv64i CPU to boot
Linux using the following options:
-cpu rv64i,rva22u64=true,rv39=true,s=true,zifencei=true
In the near future, when rva22s64 (where, 's', 'zifencei' and sv39 are
mandatory), is implemented, rv64i will be able to boot Linux loading
rva22s64 and no additional flags.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/tcg/tcg-cpu.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index d80f72a9da..f5a71b38f6 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -914,6 +914,27 @@ static void cpu_set_profile(Object *obj, Visitor *v, const
char *name,
profile->user_set = true;
profile->enabled = value;
+ for (i = 0; misa_bits[i] != 0; i++) {
+ uint32_t bit = misa_bits[i];
+
+ if (!(profile->misa_ext & bit)) {
+ continue;
+ }
+
+ if (bit == RVI && !profile->enabled) {
+ /*
+ * Disabling profiles will not disable the base
+ * ISA RV64I.
+ */
+ continue;
+ }
+
+ g_hash_table_insert(misa_ext_user_opts,
+ GUINT_TO_POINTER(bit),
+ (gpointer)value);
+ riscv_cpu_write_misa_bit(cpu, bit, profile->enabled);
+ }
+
for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) {
ext_offset = profile->ext_offsets[i];
--
2.41.0
- [PATCH v9 12/19] target/riscv/tcg: add riscv_cpu_write_misa_bit(), (continued)
- [PATCH v9 12/19] target/riscv/tcg: add riscv_cpu_write_misa_bit(), Daniel Henrique Barboza, 2023/11/02
- [PATCH v9 10/19] target/riscv/tcg: add user flag for profile support, Daniel Henrique Barboza, 2023/11/02
- [PATCH v9 18/19] target/riscv: add 'rva22u64' CPU, Daniel Henrique Barboza, 2023/11/02
- [PATCH v9 05/19] target/riscv: add zicbop extension flag, Daniel Henrique Barboza, 2023/11/02
- [PATCH v9 17/19] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion, Daniel Henrique Barboza, 2023/11/02
- [PATCH v9 19/19] target/riscv/tcg: do not support profiles for 'max' CPU, Daniel Henrique Barboza, 2023/11/02
- [PATCH v9 13/19] target/riscv/tcg: handle profile MISA bits,
Daniel Henrique Barboza <=
- [PATCH v9 16/19] target/riscv/tcg: validate profiles during finalize, Daniel Henrique Barboza, 2023/11/02
- [PATCH v9 15/19] target/riscv/tcg: honor user choice for G MISA bits, Daniel Henrique Barboza, 2023/11/02