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[PATCH v10 08/18] target/riscv: add rva22u64 profile definition
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v10 08/18] target/riscv: add rva22u64 profile definition |
Date: |
Fri, 3 Nov 2023 10:46:19 -0300 |
The rva22U64 profile, described in:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva22-profiles
Contains a set of CPU extensions aimed for 64-bit userspace
applications. Enabling this set to be enabled via a single user flag
makes it convenient to enable a predictable set of features for the CPU,
giving users more predicability when running/testing their workloads.
QEMU implements all possible extensions of this profile. All the so
called 'synthetic extensions' described in the profile that are cache
related are ignored/assumed enabled (Za64rs, Zic64b, Ziccif, Ziccrse,
Ziccamoa, Zicclsm) since we do not implement a cache model.
An abstraction called RISCVCPUProfile is created to store the profile.
'ext_offsets' contains mandatory extensions that QEMU supports. Same
thing with the 'misa_ext' mask. Optional extensions must be enabled
manually in the command line if desired.
The design here is to use the common target/riscv/cpu.c file to store
the profile declaration and export it to the accelerator files. Each
accelerator is then responsible to expose it (or not) to users and how
to enable the extensions.
Next patches will implement the profile for TCG and KVM.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/cpu.c | 32 ++++++++++++++++++++++++++++++++
target/riscv/cpu.h | 12 ++++++++++++
2 files changed, 44 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4e3ee16a25..5b78b7496d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1487,6 +1487,38 @@ Property riscv_cpu_options[] = {
DEFINE_PROP_END_OF_LIST(),
};
+/*
+ * RVA22U64 defines some 'named features' or 'synthetic extensions'
+ * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa
+ * and Zicclsm. We do not implement caching in QEMU so we'll consider
+ * all these named features as always enabled.
+ *
+ * There's no riscv,isa update for them (nor for zic64b, despite it
+ * having a cfg offset) at this moment.
+ */
+static RISCVCPUProfile RVA22U64 = {
+ .name = "rva22u64",
+ .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU,
+ .ext_offsets = {
+ CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause),
+ CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb),
+ CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin),
+ CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_zicntr),
+ CPU_CFG_OFFSET(ext_zihpm), CPU_CFG_OFFSET(ext_zicbom),
+ CPU_CFG_OFFSET(ext_zicbop), CPU_CFG_OFFSET(ext_zicboz),
+
+ /* mandatory named features for this profile */
+ CPU_CFG_OFFSET(zic64b),
+
+ RISCV_PROFILE_EXT_LIST_END
+ }
+};
+
+RISCVCPUProfile *riscv_profiles[] = {
+ &RVA22U64,
+ NULL,
+};
+
static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bf12f34082..e4d5d69207 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -66,6 +66,18 @@ const char *riscv_get_misa_ext_description(uint32_t bit);
#define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop)
+typedef struct riscv_cpu_profile {
+ const char *name;
+ uint32_t misa_ext;
+ bool enabled;
+ bool user_set;
+ const int32_t ext_offsets[];
+} RISCVCPUProfile;
+
+#define RISCV_PROFILE_EXT_LIST_END -1
+
+extern RISCVCPUProfile *riscv_profiles[];
+
/* Privileged specification version */
enum {
PRIV_VERSION_1_10_0 = 0,
--
2.41.0
- [PATCH v10 00/18] rv64i and rva22u64 CPUs, RVA22U64 profile support, Daniel Henrique Barboza, 2023/11/03
- [PATCH v10 01/18] target/riscv: create TYPE_RISCV_VENDOR_CPU, Daniel Henrique Barboza, 2023/11/03
- [PATCH v10 02/18] target/riscv/tcg: do not use "!generic" CPU checks, Daniel Henrique Barboza, 2023/11/03
- [PATCH v10 03/18] target/riscv/tcg: update priv_ver on user_set extensions, Daniel Henrique Barboza, 2023/11/03
- [PATCH v10 04/18] target/riscv: add rv64i CPU, Daniel Henrique Barboza, 2023/11/03
- [PATCH v10 05/18] target/riscv: add zicbop extension flag, Daniel Henrique Barboza, 2023/11/03
- [PATCH v10 06/18] target/riscv/tcg: add 'zic64b' support, Daniel Henrique Barboza, 2023/11/03
- [PATCH v10 08/18] target/riscv: add rva22u64 profile definition,
Daniel Henrique Barboza <=
- [PATCH v10 09/18] target/riscv/kvm: add 'rva22u64' flag as unavailable, Daniel Henrique Barboza, 2023/11/03
- [PATCH v10 10/18] target/riscv/tcg: add user flag for profile support, Daniel Henrique Barboza, 2023/11/03
- [PATCH v10 07/18] riscv-qmp-cmds.c: expose named features in cpu_model_expansion, Daniel Henrique Barboza, 2023/11/03
- [PATCH v10 11/18] target/riscv/tcg: add MISA user options hash, Daniel Henrique Barboza, 2023/11/03
- [PATCH v10 12/18] target/riscv/tcg: add riscv_cpu_write_misa_bit(), Daniel Henrique Barboza, 2023/11/03
- [PATCH v10 13/18] target/riscv/tcg: handle profile MISA bits, Daniel Henrique Barboza, 2023/11/03
- [PATCH v10 14/18] target/riscv/tcg: add hash table insert helpers, Daniel Henrique Barboza, 2023/11/03