Re: [PATCH 0/2] RISC-V: OpenTitan: Fixup ePMP and SPI interrupts

[Alistair Francis]

On Thu, Nov 2, 2023 at 10:34 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> Fixup the Ibex CPU priv version so that smepmp/epmp is correctly
> enabled and make a small change to the SPI interrupt generation to
> ensure we don't miss interrupts.
>
> Alistair Francis (2):
>   hw/ssi: ibex_spi_host: Clear the interrupt even if disabled
>   target/riscv: cpu: Set the OpenTitan priv to 1.12.0

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  hw/ssi/ibex_spi_host.c | 6 ++++--
>  target/riscv/cpu.c     | 2 +-
>  2 files changed, 5 insertions(+), 3 deletions(-)
>
> --
> 2.41.0
>