Re: [PATCH v10 08/18] target/riscv: add rva22u64 profile definition

[Jerry Shih]

On Nov 3, 2023, at 21:46, Daniel Henrique Barboza <dbarboza@ventanamicro.com> 
wrote:
> QEMU implements all possible extensions of this profile. All the so
> called 'synthetic extensions' described in the profile that are cache
> related are ignored/assumed enabled (Za64rs, Zic64b, Ziccif, Ziccrse,
> Ziccamoa, Zicclsm) since we do not implement a cache model.

> +/*
> + * RVA22U64 defines some 'named features' or 'synthetic extensions'
> + * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa
> + * and Zicclsm. We do not implement caching in QEMU so we'll consider
> + * all these named features as always enabled.
> + *
> + * There's no riscv,isa update for them (nor for zic64b, despite it
> + * having a cfg offset) at this moment.
> + */
> +static RISCVCPUProfile RVA22U64 = {
> +    .name = "rva22u64",
> +    .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU,
> +    .ext_offsets = {
> +        CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause),
> +        CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb),
> +        CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin),
> +        CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_zicntr),
> +        CPU_CFG_OFFSET(ext_zihpm), CPU_CFG_OFFSET(ext_zicbom),
> +        CPU_CFG_OFFSET(ext_zicbop), CPU_CFG_OFFSET(ext_zicboz),

Hi Daniel,

If the cache related extensions are `ignored/assumed enabled`, why don't
we export them in `riscv,isa`?
If we try to check the RVA22 profile in linux kernel running with qemu, the
isa string is not match RVA22 profile.

Thanks,
Jerry