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[PATCH for-9.0 6/7] target/riscv: add RVA22S64 profile
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH for-9.0 6/7] target/riscv: add RVA22S64 profile |
Date: |
Thu, 23 Nov 2023 16:15:31 -0300 |
The RVA22S64 profile consists of the following:
- all mandatory extensions of RVA22U64;
- priv spec v1.12.0;
- satp mode sv39;
- Ssccptr, a cache related named feature that we're assuming always
enable since we don't implement a cache;
- Other named features already implemented: Sstvecd, Sstvala,
Sscounterenw;
- the new Svade named feature that was recently added.
Most of the work is already done, so this patch is enough to implement
the profile.
After this patch, the 'rva22s64' user flag alone can be used with the
rva64i CPU to boot Linux:
-cpu rv64i,rva22s64=true
This is the /proc/cpuinfo with this profile enabled:
# cat /proc/cpuinfo
processor : 0
hart : 0
isa :
rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_zihintpause_zihpm_zfhmin_zca_zcd_zba_zbb_zbs_zkt_svinval_svpbmt
mmu : sv39
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 40 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a77118549b..d00548d164 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1559,8 +1559,48 @@ static RISCVCPUProfile RVA22U64 = {
}
};
+/*
+ * As with RVA22U64, RVA22S64 also defines 'named features'.
+ *
+ * Cache related features that we consider enabled since we don't
+ * implement cache: Ssccptr
+ *
+ * Other named features that we already implement: Sstvecd, Sstvala,
+ * Sscounterenw
+ *
+ * Named features that we need to enable: svade
+ *
+ * The remaining features/extensions comes from RVA22U64.
+ */
+static RISCVCPUProfile RVA22S64 = {
+ .name = "rva22s64",
+ .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU | RVS,
+ .priv_spec = PRIV_VERSION_1_12_0,
+ .satp_mode = VM_1_10_SV39,
+ .ext_offsets = {
+ /* rva22u64 exts and features */
+ CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause),
+ CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb),
+ CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin),
+ CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_zicntr),
+ CPU_CFG_OFFSET(ext_zihpm), CPU_CFG_OFFSET(ext_zicbom),
+ CPU_CFG_OFFSET(ext_zicbop), CPU_CFG_OFFSET(ext_zicboz),
+ CPU_CFG_OFFSET(zic64b),
+
+ /* rva22s64 exts */
+ CPU_CFG_OFFSET(ext_zifencei), CPU_CFG_OFFSET(ext_svpbmt),
+ CPU_CFG_OFFSET(ext_svinval),
+
+ /* rva22s64 named features */
+ CPU_CFG_OFFSET(svade),
+
+ RISCV_PROFILE_EXT_LIST_END
+ }
+};
+
RISCVCPUProfile *riscv_profiles[] = {
&RVA22U64,
+ &RVA22S64,
NULL,
};
--
2.41.0
- Re: [PATCH for-9.0 1/7] target/riscv: implement svade, (continued)
- [PATCH for-9.0 2/7] target/riscv: add priv ver restriction to profiles, Daniel Henrique Barboza, 2023/11/23
- [PATCH for-9.0 3/7] target/riscv/cpu.c: finalize satp_mode earlier, Daniel Henrique Barboza, 2023/11/23
- [PATCH for-9.0 4/7] target/riscv/cpu: add riscv_cpu_is_32bit(), Daniel Henrique Barboza, 2023/11/23
- [PATCH for-9.0 5/7] target/riscv: add satp_mode profile support, Daniel Henrique Barboza, 2023/11/23
- [PATCH for-9.0 6/7] target/riscv: add RVA22S64 profile,
Daniel Henrique Barboza <=
- [PATCH for-9.0 7/7] target/riscv: add rva22s64 cpu, Daniel Henrique Barboza, 2023/11/23