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[PATCH for-9.0 v12 07/18] riscv-qmp-cmds.c: expose named features in cpu
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH for-9.0 v12 07/18] riscv-qmp-cmds.c: expose named features in cpu_model_expansion |
Date: |
Fri, 24 Nov 2023 17:23:42 -0300 |
Named features (zic64b the sole example at this moment) aren't expose to
users, thus we need another way to expose them.
Go through each named feature, get its boolean value, do the needed
conversions (bool to qbool, qbool to QObject) and add it to output dict.
Another adjustment is needed: named features are evaluated during
finalize(), so riscv_cpu_finalize_features() needs to be mandatory
regardless of whether we have an input dict or not. Otherwise zic64b
will always return 'false', which is incorrect: the default values of
cache blocksizes ([cbom/cbop/cboz]_blocksize) are set to 64, satisfying
the conditions for zic64b.
Here's an API usage example after this patch:
$ ./build/qemu-system-riscv64 -S -M virt -display none
-qmp tcp:localhost:1234,server,wait=off
$ ./scripts/qmp/qmp-shell localhost:1234
Welcome to the QMP low-level shell!
Connected to QEMU 8.1.50
(QEMU) query-cpu-model-expansion type=full model={"name":"rv64"}
{"return": {"model":
{"name": "rv64", "props": {... "zic64b": true, ...}}}}
zic64b is set to 'true', as expected, since all cache sizes are 64
bytes by default.
If we change one of the cache blocksizes, zic64b is returned as 'false':
(QEMU) query-cpu-model-expansion type=full
model={"name":"rv64","props":{"cbom_blocksize":128}}
{"return": {"model":
{"name": "rv64", "props": {... "zic64b": false, ...}}}}
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/riscv-qmp-cmds.c | 30 +++++++++++++++++++++++++-----
1 file changed, 25 insertions(+), 5 deletions(-)
diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c
index 2f2dbae7c8..5ada279776 100644
--- a/target/riscv/riscv-qmp-cmds.c
+++ b/target/riscv/riscv-qmp-cmds.c
@@ -26,6 +26,7 @@
#include "qapi/error.h"
#include "qapi/qapi-commands-machine-target.h"
+#include "qapi/qmp/qbool.h"
#include "qapi/qmp/qdict.h"
#include "qapi/qmp/qerror.h"
#include "qapi/qobject-input-visitor.h"
@@ -99,6 +100,22 @@ static void riscv_obj_add_multiext_props(Object *obj, QDict
*qdict_out,
}
}
+static void riscv_obj_add_named_feats_qdict(Object *obj, QDict *qdict_out)
+{
+ const RISCVCPUMultiExtConfig *named_cfg;
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ QObject *value;
+ bool flag_val;
+
+ for (int i = 0; riscv_cpu_named_features[i].name != NULL; i++) {
+ named_cfg = &riscv_cpu_named_features[i];
+ flag_val = isa_ext_is_enabled(cpu, named_cfg->offset);
+ value = QOBJECT(qbool_from_bool(flag_val));
+
+ qdict_put_obj(qdict_out, named_cfg->name, value);
+ }
+}
+
static void riscv_cpuobj_validate_qdict_in(Object *obj, QObject *props,
const QDict *qdict_in,
Error **errp)
@@ -129,11 +146,6 @@ static void riscv_cpuobj_validate_qdict_in(Object *obj,
QObject *props,
goto err;
}
- riscv_cpu_finalize_features(RISCV_CPU(obj), &local_err);
- if (local_err) {
- goto err;
- }
-
visit_end_struct(visitor, NULL);
err:
@@ -191,6 +203,13 @@ CpuModelExpansionInfo
*qmp_query_cpu_model_expansion(CpuModelExpansionType type,
}
}
+ riscv_cpu_finalize_features(RISCV_CPU(obj), &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ object_unref(obj);
+ return NULL;
+ }
+
expansion_info = g_new0(CpuModelExpansionInfo, 1);
expansion_info->model = g_malloc0(sizeof(*expansion_info->model));
expansion_info->model->name = g_strdup(model->name);
@@ -200,6 +219,7 @@ CpuModelExpansionInfo
*qmp_query_cpu_model_expansion(CpuModelExpansionType type,
riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_extensions);
riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_experimental_exts);
riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_vendor_exts);
+ riscv_obj_add_named_feats_qdict(obj, qdict_out);
/* Add our CPU boolean options too */
riscv_obj_add_qdict_prop(obj, qdict_out, "mmu");
--
2.41.0
- [PATCH for-9.0 v12 00/18] riscv: rv64i/rva22u64 CPUs, RVA22U64 profile support, Daniel Henrique Barboza, 2023/11/24
- [PATCH for-9.0 v12 01/18] target/riscv: create TYPE_RISCV_VENDOR_CPU, Daniel Henrique Barboza, 2023/11/24
- [PATCH for-9.0 v12 02/18] target/riscv/tcg: do not use "!generic" CPU checks, Daniel Henrique Barboza, 2023/11/24
- [PATCH for-9.0 v12 05/18] target/riscv: add zicbop extension flag, Daniel Henrique Barboza, 2023/11/24
- [PATCH for-9.0 v12 03/18] target/riscv/tcg: update priv_ver on user_set extensions, Daniel Henrique Barboza, 2023/11/24
- [PATCH for-9.0 v12 04/18] target/riscv: add rv64i CPU, Daniel Henrique Barboza, 2023/11/24
- [PATCH for-9.0 v12 06/18] target/riscv/tcg: add 'zic64b' support, Daniel Henrique Barboza, 2023/11/24
- [PATCH for-9.0 v12 07/18] riscv-qmp-cmds.c: expose named features in cpu_model_expansion,
Daniel Henrique Barboza <=
- [PATCH for-9.0 v12 08/18] target/riscv: add rva22u64 profile definition, Daniel Henrique Barboza, 2023/11/24
- [PATCH for-9.0 v12 09/18] target/riscv/kvm: add 'rva22u64' flag as unavailable, Daniel Henrique Barboza, 2023/11/24
- [PATCH for-9.0 v12 10/18] target/riscv/tcg: add user flag for profile support, Daniel Henrique Barboza, 2023/11/24
- [PATCH for-9.0 v12 11/18] target/riscv/tcg: add MISA user options hash, Daniel Henrique Barboza, 2023/11/24
- [PATCH for-9.0 v12 12/18] target/riscv/tcg: add riscv_cpu_write_misa_bit(), Daniel Henrique Barboza, 2023/11/24
- [PATCH for-9.0 v12 13/18] target/riscv/tcg: handle profile MISA bits, Daniel Henrique Barboza, 2023/11/24
- [PATCH for-9.0 v12 14/18] target/riscv/tcg: add hash table insert helpers, Daniel Henrique Barboza, 2023/11/24
- [PATCH for-9.0 v12 15/18] target/riscv/tcg: honor user choice for G MISA bits, Daniel Henrique Barboza, 2023/11/24
- [PATCH for-9.0 v12 16/18] target/riscv/tcg: validate profiles during finalize, Daniel Henrique Barboza, 2023/11/24
- [PATCH for-9.0 v12 17/18] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion, Daniel Henrique Barboza, 2023/11/24