Re: [PATCH 1/2] target/riscv: Add vill check for whole vector register move instructions

[Daniel Henrique Barboza]

On 11/29/23 14:03, Max Chou wrote:
> The ratified version of RISC-V V spec section 16.6 says that
> `The instructions operate as if EEW=SEW`.
>
> So the whole vector register move instructions depend on the vtype
> register that means the whole vector register move instructions should
> raise an illegal-instruction exception when vtype.vill=1.
>
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/insn_trans/trans_rvv.c.inc | 5 +++--
>   1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 78bd363310d..114ad87397f 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3631,13 +3631,14 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r 
> *a)
>   }
>   
>   /*
> - * Whole Vector Register Move Instructions ignore vtype and vl setting.
> - * Thus, we don't need to check vill bit. (Section 16.6)
> + * Whole Vector Register Move Instructions depend on vtype register(vsew).
> + * Thus, we need to check vill bit. (Section 16.6)
>    */
>   #define GEN_VMV_WHOLE_TRANS(NAME, LEN)                             \
>   static bool trans_##NAME(DisasContext *s, arg_##NAME * a)               \
>   {                                                                       \
>       if (require_rvv(s) &&                                               \
> +        vext_check_isa_ill(s) &&                                        \
>           QEMU_IS_ALIGNED(a->rd, LEN) &&                                  \
>           QEMU_IS_ALIGNED(a->rs2, LEN)) {                                 \
>           uint32_t maxsz = (s->cfg_ptr->vlen >> 3) * LEN;                 \