Re: About RISCV’s Performance Counters and QEMU

[Atish Patra]

On Tue, Dec 5, 2023 at 4:56 AM Elio Vinciguerra <eliovinciguerra@me.com> wrote:
>
> Thanks for your answer, do you know if the working ones return actual or 
> random numbers?
>

It depends on your definition of reality :). For cycle/insteret, it
returns host_ticks by default.
For the other three events, we rely on the riscv_cpu_tlb_fill() function.

Both cases it is not close to what you would actually see in hardware.
However, we need something
to build the software ecosystem in absence of real hardware.

I don't know your requirements for running in Qemu. However, if you
can use real silicon, there are few
RISC-V hardware that have decent support for PMU.
 HiFive unleashed, Alibaba D1 and Andes AX45MP core (with inflight patches)

> And do you know if it is easily possible to implement the actual behavior of 
> other counters?
>

You mean events ? AFAIK, the problem is there is no easy way to
emulate any other event. I would be happy to be proven wrong though.
Once you find a way to emulate other events, supporting them is pretty easy.

> Regards,
> Elio
> Il 4 dic 2023, 9:30 AM +0100, Atish Patra <atishp@atishpatra.org>, ha scritto:
>
> On Fri, Dec 1, 2023 at 7:57 AM ELIO VINCIGUERRA
> <elio.vinciguerra@phd.unict.it> wrote:
>
>
> Hi everybody, I recently started using RISCV architectures, I would need a 
> way to access “hpmcounter[3-31]” registers using QEMU emulator.
>
> The kernel used for simulations is a C program, not a heavy operating system, 
> which is why I would need to access the registers mentioned before via 
> assembly.
>
> Trivially accessing any of those registers always returns zero.
>
> The question is:
> Are these registers enabled in QEMU? If not, is it possible to enable them or 
> are they hardwired to zero? How?
>
> Trying to access the registers “cycle”, “instret” and “time” the values come 
> out to be non-zero, which is why I think it is also possible to enable 
> “hpmcounter[3-31]”, but the mode of operation is unknown to me, can anyone 
> help me?
>
>
> Yes. You can use all the hpmcounters[3-31]. By default,
> hpmcounter[3-18] are enabled. You can modify the set of counters using
> pmu-mask cpu property.
> https://gitlab.com/qemu-project/qemu/-/blob/master/target/riscv/cpu.c?ref_type=heads#L1467
>
> However, upstream Qemu doesn't support a lot of PMU events. It only
> supports 3 cache related events apart from cycle/instret.
>
> Here are the events it supports.
> https://gitlab.com/qemu-project/qemu/-/blob/master/target/riscv/pmu.c?ref_type=heads#L36
>
> Regards,
> Elio
>
>
>
>
> --
> Regards,
> Atish



-- 
Regards,
Atish